SO 51 X3 X2 X1 INPIT XO INPUT ve 4 inst5| LON De Figure 4. Schematic of 4-1 Multiplexer 4000 AND: inst AND3 inste AND: inst AND: inst ORA insts OUTPUNY

Introductory Circuit Analysis (13th Edition)
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ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
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Determine the logic expression for the output Y as a function of the inputs
Creating a 4-1 Multiplexer using VHDL
Now you are ready to enter your 4-1 multiplexer design using VHDL and the Quartus editor. The
schematic for a 4-1 multiplexer is shown in Figure 4. Determine the logic expression for the
output Y as a function of the inputs S1, SO, X3, X2, X1, and XO.
SO
$1
X3
X2
X1
INDILIT
INPUT
INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC
AND:
inst
AND
inste
AND3
instr
AND3
OR4
inste
insts
OUTPU
Y
хо
Figure 4. Schematic of 4-1 Multiplexer
Using a dataflow architecture, create the VHDL design for a 4-1 multiplexer.
Compile the design and correct any errors. The process for compiling a simulating a VHDL
design is the same as for schematic entry designs.
Transcribed Image Text:Creating a 4-1 Multiplexer using VHDL Now you are ready to enter your 4-1 multiplexer design using VHDL and the Quartus editor. The schematic for a 4-1 multiplexer is shown in Figure 4. Determine the logic expression for the output Y as a function of the inputs S1, SO, X3, X2, X1, and XO. SO $1 X3 X2 X1 INDILIT INPUT INPUT VCC INPUT VCC INPUT VCC INPUT VCC AND: inst AND inste AND3 instr AND3 OR4 inste insts OUTPU Y хо Figure 4. Schematic of 4-1 Multiplexer Using a dataflow architecture, create the VHDL design for a 4-1 multiplexer. Compile the design and correct any errors. The process for compiling a simulating a VHDL design is the same as for schematic entry designs.
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