Quiz 4 Adders and Multiplexers and Decoders_ EEE 120_ Digital Design Fundamentals (2024 Spring)

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Arizona State University *

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120

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Electrical Engineering

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Apr 3, 2024

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Quiz 4 Adders and Multiplexers and Decoders Due Mar 3 at 11:59pm Points 75 Questions 13 Available until Mar 3 at 11:59pm Time Limit 45 Minutes Allowed Attempts 2 Instructions Attempt History Directions 1. Take the quiz after completing the reading and activities of Adders, Multiplexers,decoder and PLDs. 2. You will have 4 5 minutes time to complete each attempt of the quiz. 3. You will have two attempts. Will keep the average score of the two attempts. 4. There are no make-up opportunities if the quiz is not completed by due date. 5. The quiz is open books and notes. Take the Quiz Again
Attempt Time Score LATEST Attempt 1 19 minutes 75 out of 75 Answers will be shown after your last attempt Score for this attempt: 75 out of 75 Submitted Mar 2 at 11:50pm This attempt took 19 minutes. Question 1 5 / 5 pts the carry-out is ignored that carry-out will always be HIGH the same as if the carry-in is tied LOW since the least significant carry-in is ignored a one will be added to the final result Question 2 5 / 5 pts Half adders can handle only single-digit numbers. Full adders have a carry input capability. Nothing basically; full-adders are made up of two half-adders. Full adders can handle double-digit numbers. Question 3 5 / 5 pts inverting the carry-in. inverting the B inputs inverting the output. For a 4-bit parallel adder, if the carry-in is connected to a logical HIGH, the result is: What is the major difference between half-adders and full-adders? One way to make a four-bit adder perform subtraction is by:
grounding the B inputs. Question 4 5 / 5 pts True False Question 5 5 / 5 pts data selector encoder decoder code converter Question 6 5 / 5 pts four data inputs and four select inputs two data inputs and four select inputs two data inputs and two select inputs four data inputs and two select inputs Question 7 5 / 5 pts True False Half-adders can be combined to form a full-adder with no additional gates using Boolean Algebra equations. A multiplexer is also known as a(n) A four-line multiplexer must have A demultiplexer has multiple inputs and a single output.
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Question 8 5 / 5 pts True False Question 9 5 / 5 pts True False Question 10 5 / 5 pts counter comparator demultiplexer multiplexer Question 11 10 / 10 pts A demux basically reverses the function of a mux. A 9-1 Multiplexer requires 9 selectors A device which places its input data onto one of several outputs is a For the following circuit, what are the values of S S S S and OF given the following inputs: 3 2 1 0
OF =1 and S3 S2 S1 S0 = 1 1 1 0 OF =0 and S3 S2 S1 S0 = 1 1 1 0 OF =0 and S3 S2 S1 S0 = 0 1 0 0 OF =1 and S3 S2 S1 S0 = 0 1 0 0 Question 12 10 / 10 pts For the following circuit, what are the values of S S S S and OF given the following inputs: 3 2 1 0
OF =1 and S3 S2 S1 S0 = 1 1 1 0 OF =1 and S3 S2 S1 S0 = 0 1 0 0 OF =0 and S3 S2 S1 S0 = 0 1 0 0 OF =0 and S3 S2 S1 S0 = 1 1 1 0 Question 13 5 / 5 pts Does this circuit work as an always-enabled 2:4 Decoder?
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True False Quiz Score: 75 out of 75