project 1 (1)

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Stony Brook University *

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Electrical Engineering

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Apr 3, 2024

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ECE 3150 – Spring 2024 Project 1 This project has two parts. In part A you will work on schematic design and simulations. In Part B, you will design the layout of digital CMOS gates and perform DRC and LVS checks. Unless otherwise mentioned, assume that the V DD =1V. You will use both PMOS and NMOS transistors with threshold VTL threshold voltages in the FreePDK45 library. You will need to submit a single PDF file for the entire project. It will be easier for you to work on a Word File where you can paste screen-captures and write down your answers to each question. Your final submission should be a single PDF with different sections titled for each Part/Section. Be sure to include your name, GTID, date, and short description in EVERY schematic, simulation, and layout. Part A (1) Design an inverter with the standard VTL NMOS transistor that is available to you in the 45nm CMOS process technology library. Use simulations to determine the width of the PMOS transistor of the inverter such that the trip point V M is at V DD /2. You will need to perform DC analysis and generate the voltage transfer characteristics to size the PMOS transistor. What to submit (In a section titled “Problem 1”): As a part of this problem, submit the following: a) A picture of the inverter schematic. Make sure to include your name, gtid, date, and description on your schematic using the text tool in Cadence b) The sizes of the NMOS and PMOS transistors c) A picture of the Voltage Transfer Characteristics (VTC), showing Vm = Vdd/2. Make sure to include your name, gtid, date, and description on your waveform using the text tool in Cadence (2) From the VTC, obtain V OL , V OH , V IL , V IH , N ML and N MH . Find the Gain of the inverter at V M . What to submit (In a section titled “Problem 2”): Write down the values of the parameters (above). No screen capture is required. (3) Create a symbol of the inverter. Now perform transient simulations to obtain the highto- low delay and low-to-high delay of the inverter when it is driving a Fan-Out of 1, 2, 4 and 8 Inverters. Propagation delays should be taken at 50% vdd values. What to submit (In a section titled “Problem 3”):

a) Submit screenshots of each fan out schematic. Make sure to include your name, gtid, date, and description on your schematic using the text tool in Cadence b) Submit picture of the simulation window showing the input signal and the output transient response for the fan out 8 condition. Make sure to include your name, gtid, date, and description on your waveform using the text tool in Cadence c) Write down the high-to-low and low-to-high delays for all the four Fan-Out conditions. (4) Now consider the FO1 inverter. Apply an input square pulse of frequency (F) and obtain the total power dissipated by the inverter through transient simulations. Generate the results for F = 50 MHz, 100 MHz, 200 MHz, 400 MHz. Perform all the simulations, simulate till 200ns. What to submit (In a section titled “Problem 4”): a) Plot the power dissipated by the FO1 inverter as a function of the input frequency (F). You can use Excel to create this plot. What conclusions can you draw from this data? (5) Now design a 2-input NAND Gate (NAND2) with the same PMOS width as that of the inverter in Problem -1. Size the width of the NMOS to be twice that of the inverter. Create a symbol of the NAND gate. Now perform transient simulation of the NAND gate using a single inverter from the previous design as the load. This represents the FO1 condition for the NAND2 gate. To obtain high-to-low or low-to-high transitions at the output, keep one of the inputs fixed at “1”. Switch the second input from either “0” to “1” or “1” to “0”. Make sure to change both inputs to test all four input/output combinations. Propagation delays should be taken at 50% vdd values. What to submit (In a section titled “Problem 5”): a) Submit a screenshot of your NAND2 gate schematic. Make sure to include your name, gtid, date, and description on your schematic using the text tool in Cadence b) Submit a picture of the simulation window showing the input signal and the output transient response for FO1 NAND2 gate. Make sure to show all 4 input/output combinations. Make sure to include your name, gtid, date, and description on your waveform using the text tool in Cadence c) Write down the high-to-low and low-to-high delays for the NAND2 gate using the FO1 condition. (6) Now design a 2-input XOR Gate (XOR2) using the same transistor sizes as problem 5. Show in simulation that your gate works as expected by using stimuli for your input pins to alternate inputs and capture the output of the gate.

What to submit (In a section titled “Problem 6”): a) Submit a screenshot of your XOR2 gate schematic. Make sure to include your name, gtid, date, and description on your schematic using the text tool in Cadence b) Submit a screenshot of your XOR2 transient response. Make sure to show all 4 input/output combinations. Make sure to include your name, gtid, date, and description on your waveform using the text tool in Cadence. Part B 1. Now that the schematic design has been completed, lay out your inverter, NAND2, and XOR2 digital gates cells following a standard cell library format. Pay particular attention to the cell height, V DD and GND lines and N-WELLs. The cell height is the distance from the top of the V DD line to the bottom of the GND line. Use a cell height of UP TO 2um. ALL GATES SHOULD USE THE SAME CELL HEIGHT. The cells in the library should only use local metals, i.e., up to metal layer 2. The cells should abut – i.e., when you place the inverter and the NAND2 gates next to each other, there should be no DRC error. Make sure to insert a psub tap and an n-well tap for your layouts. 2. Make sure that the cell layouts pass DRC and LVS . What to submit (In a section called “Part B”): a) A picture of the layout for the inverter, NAND2, and XOR2 gates. This should be 3 separate screenshots. Make sure to include your name, gtid, date, and description on each layout using the text tool in Cadence b) A picture of the inverter and the NAND2 gates placed next to each other showing that the VDD and GND lines and the N-Wells are continuous. c) Report the heights and widths of each gate. You can include a screenshot if you’d like. d) A picture of the LVS window and the DRC window showing that all designs are error-free. You should have this for each gate

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