Lab 7
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Pedro Leon Lab 7
1. What are the Inputs to the ROM and how many rows must the ROM have?
The inputs generally consist of an address bus and, occasionally, control signals. The ROM's capacity, expressed in terms of the number of rows or entries, is directly tied to the width of the address bus. The address bus width dictates the range of unique addresses that can be employed to access data stored within the ROM.
2. How many outputs and how many columns must the ROM have?
The number of outputs can vary based on the data stored at each address, and the number of columns is determined by the word size of the ROM.
3. How many effective address lines?
The number of effective address lines in a ROM is equivalent to the width of the ROM's address bus.
4. Write the equations you could use if you implemented it with 2 FF and coded the 3 States 00, 01 and 10 for A and B FF.
It will be somethingg like this A_next = ~A & B , B_next = A & ~B
5. Did you provide for Q and Q’ outputs from your FF’s? Why would this be helpful?
Yeah since it can offer flexibility and signal accessibility, and is essential for various logic and control operations within a circuit.
5. Which method required more resources on the FPGA (check the usage report)?
Creating multiple instances of a smaller counter can lead to higher resource consumption because it involves additional overhead related to control logic and the connections required between these counter instances.
6. Which method did you find was easier to do?
Using a counter with a parallel load I believe that it was the most straightforward or easier.
7. Paste in your code.
module ROM(
output [7:0] LED,
output [4:0] Ao,
input [7:0] D,
input [4:0] A,
input Clear,
input Load,
input CLK);
reg [7:0] Store [0:31];
initial begin Store[0]<=8'b00000000;
Store[1]<=8'b00000000;
Store[2]<=8'b00000000;
Store[3]<=8'b00000000;
Store[4]<=8'b00000000;
Store[5]<=8'b00000000;
Store[6]<=8'b00000000;
Store[7]<=8'b00000000;
Store[8]<=8'b00000000;
Store[9]<=8'b00000000;
Store[10]<=8'b00000000;
Store[11]<=8'b00000000;
Store[12]<=8'b00000000;
Store[13]<=8'b00000000;
Store[14]<=8'b00000000;
Store[15]<=8'b00000000;
Store[16]<=8'b00000000;
Store[17]<=8'b00000000;
Store[18]<=8'b00000000;
Store[19]<=8'b00000000;
Store[20]<=8'b00000000;
Store[21]<=8'b00000000;
Store[22]<=8'b00000000;
Store[23]<=8'b00000000;
Store[24]<=8'b00000000;
Store[25]<=8'b00000000;
Store[26]<=8'b00000000;
Store[27]<=8'b00000000;
Store[28]<=8'b00000000;
Store[29]<=8'b00000000;
Store[30]<=8'b00000000;
Store[31]<=8'b00000000;
end
assign LED = Store[A];
assign Ao = A;
always @(posedge CLK)
begin if(Clear)
begin
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Store[A] <= 8'b00000000;
end
else if(Load)
begin
Store[A] <= D;
end
end
endmodule
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STR r1, [r0, # 4]
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