Lab 10
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Laredo College *
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1449
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Electrical Engineering
Date
Apr 3, 2024
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docx
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Uploaded by CaptainRain803
Pedro Leon
Lab 10
1. In this lab we used Xilinx’s Clocking Wizard IP to generate a clock, instead of using a clock divider for our pixel clock.
a) What are some advantages of using an IP?
Timing precision/tolerances, Faster/easier to implement than typing additional, separate modules.
b) What are some reasons to avoid the use of combinational clock dividers for timing?
Reduced timing precision due to inertial delays associated with gates/combinational logic.
c) What is a good practice for clock dividers discussed in this lab?
Use for lower frequency applications.
2. Suppose we wanted to use VGA at a resolution of 800x600 @ 60Hz. What would be the required pixel clock for this?
The required pixel clock would be 37.152 MHz
3. Draw a state transition table for the final part of the lab, where we go from red to green to blue
Present State
Next State
Red
Green
Blue
00
01
1
0
0
01
10
0
1
0
10
01
0
0
1
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