Lab 9

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Electrical Engineering

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Apr 3, 2024

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Pedro Leon Lab 9 1. What are the limits on how fast the comparator works? How could the design be modified to make it work faster? Some of the limits on how fast the comparator works include the number of bits compared and the inertial delay of the combinational logic gates. The design can be modified to work faster by reducing the number of bits to compare or number of gates. 2. Could you extend the design to more bits? Yes 3. Note: that if A=1001 and B=1010 what are the results of these various tests: If (A && B) = T or F ; if(A&B) = T or F ; Now with A=0000 and B=0000: If(A == B) = T or F; if (A=B) = T or F 4. How many bits of information must be sent from one module to the next of the 1 bit comparator module, how many wires does this take? 2 bits of information are sent from 1 1-bit module to the next module. 2 wires per module. 5. List 2 different ways you could write the Verilog code: List on at the behavioral level and one at the Register Transfer Level (RTL) with the logic equations you developed. Data is transformed as it is passed from register to register. Behavioral code is higher-level and usually can't be synthesized. Constructs like loops, delays, and "initial" statements are behavioral. RTL code is lower-level and is intended to be synthesized. 6. List the truth table for your 1 bit comparator. How many outputs must connect from one cell to the next? How many different outcomes are there for each comparison?

A B A < B A > B A = B 0 0 F F T 0 1 T F F 1 0 F T F 1 1 F F T 7. Paste in your code: module Lab_9( input CLK, input [7:0] SW, output [15:0] LED, output [7:0] SSEG_CA, output [7:0] SSEG_AN ); parameter width1 = 100000000; parameter width2=10000; wire [3:0] GT,LT; wire [7:0] Sarray [0:7]; wire [63:0] Pass_Array; wire [7:0] Seg_val0; wire Clk_Slow, Clk_Multi; wire [7:0] Seg_valA; wire [7:0] Seg_valB; wire [7:0] Seg_valResult; assign LED[7:0] = SW[7:0]; assign LED[12:8]= 1'b0; Clk_Divide # (width1,width2) IN0 (CLK, Clk_Slow, Clk_Multi);

Comparator IN1 (SW[7],SW[3],1'b0,1'b0,GT[3],LT[3]); Comparator IN2 (SW[6],SW[2],GT[3],LT[3],GT[2],LT[2]); Comparator IN3 (SW[5],SW[1],GT[2],LT[2],GT[1],LT[1]); Comparator IN4 (SW[4],SW[0],GT[1],LT[1],GT[0],LT[0]); Digit_Set_Segs IN5 (SW[3:0],1'b0,Seg_valB); assign Sarray [0] = Seg_valB; Digit_Set_Segs IN6 (SW[7:4],1'b0,Seg_valA); assign Sarray [1] = Seg_valA; assign LED[15] = GT[0]; assign LED [13] = LT[0]; assign LED [14] = (!GT[3:0] && !LT[3:0]); assign Seg_valResult = (GT[3:0])? ~(8'b01111101):((LT[3:0])? ~(8'b00111000):~(8'b01111001)); assign Sarray [7]= Seg_valResult; assign Sarray [2] = 8'hFF; assign Sarray [3] = 8'hFF; assign Sarray [4] = 8'hFF; assign Sarray [5] = 8'hFF; assign Sarray [6] = 8'hFF; assign Pass_Array = {Sarray[0],Sarray[1],Sarray[2],Sarray[3],Sarray[4],Sarray[5],Sarray[6],Sarray[7]}; Display_Digit IN7 (Pass_Array, Clk_Multi, SSEG_CA, SSEG_AN); endmodule module Comparator ( input X, input Y, input GTn, input LTn, output reg GTn1,

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