exam2_sol

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California State University, Northridge *

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526

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Electrical Engineering

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Oct 30, 2023

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docx

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Top Level, Page One module x2s20 #(WIDTH = 16) (input CLK, RST, RW, SD, input [1:0] ADDR, inout wire [WIDTH - 1 : 0] DATA, output PWM); /* Addressable registers: PERIOD: COUNT returns to zero upon match HIGHTIME: set PWM to logic 1 upon COUNT match for double edged LOWTIME: set PWM to logic 0 upon COUNT match for both single and double PRESCALE: PRECOUNT returns to 0 upon match * / wire [WIDTH- 1 : 0] PRECOUNT, COUNT, PERIOD, PRESCALE, HIGHTIME, LOWTIME, SELDATA; wire [3:0] ONEHOT; assign DATA = RW ? SELDATA :'bZ;

Top Level, Page 2 DECODE DEC(ADDR, ONEHOT); SELECT #(.WIDTH(WIDTH)) SEL(ADDR, PERIOD, PRESCALE, HIGHTIME, LOWTIME, SELDATA); SCALE_REG #({.WIDTH(WIDTH)) SR1(CLK, ONEHOT[0], DATA, PERIOD); SCALE_REG #{.WIDTH(WIDTH)) SR2(CLK, ONEHOT[1], DATA, PRESCALE); SCALE_REG #{.WIDTH(WIDTH)) SR3(CLK, ONEHOT[2], DATA, HIGHTIME); SCALE_REG #{.WIDTH(WIDTH)) SR4(CLK, ONEHOT[3], DATA, LOWTIME); SCALE_CNT #{.WIDTH(WIDTH)) SC1(CLK, RST, 1'b1, PRESCALE, PRECOUNT); SCALE_CNT #({WIDTH(WIDTH)) SC2(CLK, RST, (PRECOUNT == 0), PERIOD, COUNT); PWMOUT #(WIDTH(WIDTH)) PW1(CLK, sd, COUNT, HIGHTIME, LOWTIME, PWM); b Scalable Register module SCALE_REG #(WIDTH = 16) (input CLK, EN, input [WIDTH-1: 0] DIN, output reg [WIDTH- 1 : 0] DOUT); always_ff @(posedge CLK) if (EN) DOUT <= DIN; else DOUT <= DOUT; endmodule

Scalable Counter module SCALE_CNT #(WIDTH = 16) (input CLK, RST, EN, input [WIDTH-1: 0] MATCH, output reg [WIDTH- 1 : 0] COUNT); always_ff @(posedge CLK, negedge RST) if (IRST) COUNT <= 0; else if (MATCH == COUNT) COUNT <=0; else if (EN) COUNT <= COUNT + 1; else COUNT <= COUNT; endmodule Provide Enables for Registers module DECODE (input [1:0] ADDR, output reg [3:0] ONEHOT); always_comb case (ADDR) 0: ONEHOT =4'b0001; 1: ONEHOT = 4'b0010; 2: ONEHOT =4'b0100; default: ONEHOT = 4'b1000; endcase endmodule

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Selector for Reading Registers module SELECT #(WIDTH = 16) (input [1:0] ADDR, input [WIDTH-1: 0] A, B, C, D, outputreg [WIDTH- 1 : 0] DATA); always_comb case (ADDR) 0: DATA= A; 1: DATA=B; 2: DATA=C; default: DATA=D; N endcase endmodule PWM Output Block module PWMOUT #(WIDTH = 16) (input CLK, SD, input [WIDTH -1 : 0] COUNT, HIGHTIME, LOWTIME, output reg PWM); always_ff @(posedge CLK) if (SD) //Double Edge if (COUNT == LOWTIME) PWM <= 1'b0; //if high and low are equal, low wins else if (COUNT == HIGHTIME) PWM <= 1'b1; else if (LOWTIME > HIGHTIME && COUNT ==0) PWM <= 1'b0; else if (HIGHTIME > LOWTIME && COUNT ==0) PWM <= 1'b1; else PWM <= PWM; else //Single Edge if (LOWTIME ==0) PWM <= 1'b0; else if (COUNT ==0) PWM <= 1'b1; else if (COUNT == LOWTIME) PWM <= 1'b0; else PWM <= PWM; endmodule

Test Bench, Page One module tb_x2s20; parameter WIDTH = 32; bit CLK, RST; reg RW, SD; reg [1:0] ADDR; reg [WIDTH- 1 : 0] DATAREG; wire [WIDTH - 1 : 0] DATA; %2520 #(.WIDTH(WIDTH)) UUT(CLK, RST, RW, SD, ADDR, DATA, PWM); assign DATA = RW ? 'z: DATAREG; initial forever #1 CLK = ~CLK;

Test Bench, Page Two initial begin RW = 0; ADDR = 0; DATAREG = 10; SD = 1'b1; //SET PERIOD #10 ADDR = 1; DATAREG = 2; //set PRESCALE #2 ADDR = 2; DATAREG = 3; //SET HIGHTIME #2 ADDR = 3; DATAREG = 4; //SET LOWTIME #2 RST=1'b0; #2RST=1'b1; end endmodule Verifying the design per spec would have required storing 10,000 in the period register, the prescale register or split between them. Not a theoretical problem but would have made the simulation take a long time betweenvisible output changes. PWM in Operation 18] Wave - Default s + VYNV YV

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