T9. Tutorial Answers

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Swinburne University of Technology *

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EEE20001

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Electrical Engineering

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Oct 30, 2023

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Digital Electronics - Tutorial 32 of 46 Tutorial 9 Solution Q1) P1 : process ( clock ) begin if rising_edge ( clock ) then t <= w or x ; b <= t and y ; end if ; end process P1 ; Note: Two FFs. The assigments to t and b are separated by a clock cycle! P2 : process ( clock , t , y ) begin if rising_edge ( clock ) then t <= w or x ; end if ; b <= t and y ; end process P2 ; Q2) --==================================================== -- Two example shift register architectures -- entity ShiftRegister is Port ( reset : in STD_LOGIC ; clock : in STD_LOGIC ; shiftEn : in STD_LOGIC ; loadEn : in STD_LOGIC ; serialIn : in STD_LOGIC ; d : in STD_LOGIC_VECTOR ( 7 downto 0 ); q : out STD_LOGIC_VECTOR ( 7 downto 0 ) ); end ShiftRegister ;

Digital Electronics - Tutorial 33 of 46 Q2) cont. --================================================= -- 8-bit SR -- Asynchronous reset -- Asynchronous load -- Synchronous shift (obviously) architecture Behavioral of ShiftRegister is signal tq : STD_LOGIC_VECTOR ( 7 downto 0 ); begin q <= tq ; process ( reset , loadEn , d , clock ) begin if ( reset = ' 1 ' ) then -- asynchronous reset tq <= ( others => ' 0 ' ); elsif ( loadEn = ' 1 ' ) then -- asynchronous load tq <= d ; elsif rising_edge ( clock ) then if ( shiftEn = ' 1 ' ) then – - synchronous shift left tq <= tq ( 6 downto 0 ) & serialIn ; -- or tq <= tq(tq'left-1 downto tq'right) & serialIn; end if ; end if ; end process ; end Behavioral ; --================================================= -- 8-bit SR -- Asynchronous reset -- Synchronous load -- Synchronous shift (obviously) architecture Behavioral2 of ShiftRegister is signal tq : STD_LOGIC_VECTOR ( 7 downto 0 ); begin q <= tq ; process ( reset , clock ) begin if ( reset = ' 1 ' ) then -- asynchronous reset tq <= ( others => ' 0 ' ); elsif rising_edge ( clock ) then if ( loadEn = ' 1 ' ) then -- synchronous load tq <= d ; elsif ( shiftEn = ' 1 ' ) then -- synchronous shift left tq <= tq ( 6 downto 0 ) & serialIn ; -- or tq <= tq(tq'left-1 downto tq'right) & serialIn; end if ; end if ; end process ; end Behavioral2 ;

Digital Electronics - Tutorial 34 of 46 Q3) --=================================================================== -- dieCounter.vhdl -- -- A counter to produce a roll in the range 1 .. 6 (like a die) -- -- Revision History --=================================================================== -- 6/4/17 - Created - pgo --=================================================================== library ieee ; use ieee . std_logic_1164 . ALL ; use ieee . numeric_std . all ; entity dieCounter is Port ( reset : in std_logic ; clock : in std_logic ; roll : in std_logic ; count : out std_logic_vector ( 2 downto 0 ) ); end dieCounter ; architecture Behavioural of dieCounter is signal dieCount : unsigned ( 2 downto 0 ); begin count <= std_logic_vector ( dieCount ); -- Produce dieCount sequence from 1 ... 6 counter : process ( reset , clock ) begin if ( reset = ' 1 ' ) then dieCount <= "001" ; -- start count from 1 elsif ( clock' event and ( clock = ' 1 ' )) then if ( roll = ' 1 ' ) then -- rolling if ( dieCount >= "110" ) then dieCount <= "001" ; -- wrap count else dieCount <= dieCount + "001" ; end if ; end if ; end if ; end process ; end Behavioural ;

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Digital Electronics - Tutorial 35 of 46 Q4) --=================================================================== -- Linear Feedback Shift Register -- Generates a Pseudo-random bit sequence of length 127 bits -- -- Uses the Polynomial: X7 <= X3 xor X0 -- -- Revision History --=================================================================== -- 6/ 5/06 - Created - pgo --=================================================================== library IEEE ; use IEEE . STD_LOGIC_1164 . ALL ; use IEEE . STD_LOGIC_ARITH . ALL ; use IEEE . STD_LOGIC_UNSIGNED . ALL ; entity LFSR is Port ( reset : in STD_LOGIC ; clock : in STD_LOGIC ; prbs : out STD_LOGIC ); end LFSR ; architecture Behavioral of LFSR is signal shiftReg : std_logic_vector ( 6 downto 0 ); begin prbs <= shiftReg ( 0 ); LFSRProcess : process ( reset , clock ) begin if ( reset = ' 1 ' ) then shiftReg <= ( 1 => ' 1 ' , others => ' 0 ' ); elsif rising_edge ( clock ) then shiftReg ( shiftReg' left) <= ( shiftReg ( 3 ) xor shiftReg ( 0 )); shiftReg ( shiftReg' left- 1 downto 0 ) <= shiftReg ( shiftReg' left downto 1 ); end if ; end process LFSRProcess ; end Behavioral ; Q5) Deleted

Digital Electronics - Tutorial 36 of 46 Q6) Behavioural architecture (occupies 2 slices of FPGA) library IEEE; use IEEE.STD_LOGIC_1164. ALL ; entity StateMachine is Port ( reset : in std_logic ; clock : in std_logic ; X1 : in std_logic ; X2 : in std_logic ; f : out std_logic ); end StateMachine; architecture behavioural of StateMachine is type StateType is ( idle , ph1 , ph2 , done ); signal state , nextState : StateType ; begin sync: process ( reset , clock ) begin if ( reset = '1' ) then state <= idle ; elsif (rising_edge( clock )) then state <= nextState ; end if ; end process sync; comb: process ( state , X1 , X2 ) begin -- Default values f <= '0' ; -- State machine logic case state is when idle => if ( X1 = '0' ) and ( X2 = '0' ) then -- OR if (X1&X2 = "00") then etc nextState <= idle ; else nextState <= ph1 ; end if ; when ph1 => if ( X1 = '0' ) then nextState <= ph1 ; else nextState <= done ; end if ; when ph2 => f <= '1' ; if ( X1 = '1' ) and ( X2 = '1' ) then nextState <= ph2 ; else nextState <= idle ; end if ; when done => if ( X1 = '1' ) and ( X2 = '1' ) then nextState <= ph2 ; else nextState <= done ; end if ; end case ; end process comb; end architecture behavioural;

Digital Electronics - Tutorial 37 of 46 Q7) Structural architecture (occupies 7 slices of FPGA – but not optimised!) This is not a sensible way to do a state machine. It would only be a reasonable approach if you had the circuit of the SM available (as in this question) and simply wanted the implementation with the minimum of work. library IEEE; use IEEE.STD_LOGIC_1164. ALL ; entity StateMachine is Port ( reset : in std_logic ; clock : in std_logic ; X : in std_logic_vector ( 2 downto 1 ); F : out std_logic ); end StateMachine; architecture pseudoStructural of StateMachine is signal D , Q : std_logic_vector ( 2 downto 1 ); begin -- Build flip flops from schematic sync: process ( reset , clock ) begin if ( reset = '1' ) then Q <= ( others => '0' ); elsif (rising_edge( clock )) then Q <= D ; end if ; end process sync; -- Build logic from schematic comb: process ( Q , X ) begin D ( 1 ) <= ( X ( 1 ) and X ( 2 ) and Q ( 1 )) or ( Q ( 1 ) and Q ( 2 )) or ( X ( 1 ) and Q ( 2 )); D ( 2 ) <= (( X ( 1 ) or X ( 2 )) and not Q ( 1 )) or ( Q ( 2 ) and ( not X ( 1 ) or not X ( 2 ))); F <= Q ( 1 ) and not Q ( 2 ); end process comb; end architecture pseudoStructural;

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