T5. Tutorial Answers

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EEE20001

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Oct 30, 2023

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Digital Electronics - Tutorial 12 of 46 Tutorial 5 Solution Q1) Not provided Q2) Draw circuit and label input values. Determine steady state (initial) conditions. Propagate the input change through the circuit using the delays in the VHDL statements. R changes to 1 @ 112 ns. Q3) Given that A="00101101" and B="10011", determine the value of: F <= (not B & "0111") or (A & '1') and ('1' & A); F <= (not "10011" & "0111") or ("00101101" & '1') and ('1' & "00101101"); F <= ("01100" & "0111") or ("001011011") and ("100101101"); F <= "011000111" or "001011011" and "100101101"; F <= ("011000111" or "001011011") and ("100101101"); -- left to right! F <= "011011111" and "100101101"; F <= "000001101"; Q4) library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ThreeGates is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; x : out STD_LOGIC; y : out STD_LOGIC); end ThreeGates; architecture Behavioral of ThreeGates is signal t : std_logic; begin t <= not b; -- depends how pedantic you want to be! x <= a and t; -- or x <= a and not b; y <= c and t; -- or y <= c and not b; end Behavioral;
Digital Electronics - Tutorial 13 of 46 Q5) library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity TruthTable is Port ( a : in STD_LOGIC; b : in STD_LOGIC; w : out STD_LOGIC_VECTOR (3 downto 0); x : out STD_LOGIC); end entity TruthTable; architecture Behavioral of TruthTable is signal t : std_logic_vector(1 downto 0); begin t <= a & b; -- Note it would be better to use selected assignment as -- alternatives are mutually exclusive (not covered yet). w <= "0000" when t = "00" else "1010" when t = "01" else "1100" when t = "10" else "1001" when t = "11" else "XXXX"; -- needed for other 'std_logic' values e.g. 'U','Z' etc; x <= '0' when t = "00" else '0' when t = "01" else '1' when t = "10" else '0' when t = "11" else 'X'; -- needed for other 'std_logic' values e.g. 'U','Z' etc; end architecture Behavioral; Q6) Deleted.
Digital Electronics - Tutorial 14 of 46 Q7) F 1 = A’B’E + AF + D’E’ F 2 = B’CD’E + A’ Q8) F 1 = AB’D + A’C’ + BC + C’D’ F 2 = A’C’ + AC + C’D’ F 3 = CD + A’C’ + AB’D Peter O'Donoghue 03/04/2017 A A A’ A’ B B B’ B’ C C C’ C’ D D D’ D’ E E E’ E’ F F F’ F’ A’ AF D’E’ B’C A’ 0 F 1 F 2 A A A’ A’ B B B’ B’ C C C’ C’ D D D’ D’ E E E’ E’ F F F’ F’ AB’D A’C’ BC C’D’ AC CD F 1 F 2 F 3
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