T10. Tutorial Answers

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Swinburne University of Technology *

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EEE20001

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Electrical Engineering

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Oct 30, 2023

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Digital Electronics - Tutorial 38 of 46 Tutorial 10 Solution Q1) Vending Machine (Not provided) Q2) 3-bit Up/Down counter with count enable (Updated to use ieee.numeric_std ) -------------------------------------------------------------------------------- -- Tutorial 10 Q2) 3-bit up/down counter module with count enable -------------------------------------------------------------------------------- library IEEE; use ieee.std_logic_1164. all ; use ieee.numeric_std. all ; entity count3 is Port ( reset : in std_logic ; clock : in std_logic ; countEn : in std_logic ; direction : in std_logic ; q : out std_logic_vector ( 2 downto 0 ) ); end entity count3; architecture Behavioral of count3 is signal tq : signed ( 2 downto 0 ); begin q <= std_logic_vector ( count ); -- Convert value to std_logic_vector sync: process ( reset , clock ) begin if ( reset = '1' ) then count <= ( others => '0' ); elsif (rising_edge( clock )) then if ( countEn = '1' ) then if ( direction = '1' ) then count <= count + "1" ; else count <= count - "1" ; end if ; end if ; end if ; end process sync; end architecture Behavioral;

Digital Electronics - Tutorial 39 of 46 3-bit Up/Down counter with count enable (Updated to use ieee.numeric_std ) -------------------------------------------------------------------------------- -- Tutorial 10 Q3) 3-bit ‘automatic’ up/down counter module with count enable -- Also a good example of using enumerated types outside of state machines -------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164. all ; use IEEE.numeric_std. all ; entity count3 is Port ( reset : in std_logic ; clock : in std_logic ; countEn : in std_logic ; q : out std_logic_vector ( 2 downto 0 ) ); end entity count3; architecture Behavioral of count3 is signal count : unsigned ( 2 downto 0 ); -- It is common to use unsigned for counters type DirectionType is ( up , down ); -- Example use of enumerated type signal direction : DirectionType ; -- Easier to 'read' begin q <= std_logic_vector ( count ); -- Convert value to slv for output sync : process ( reset , clock ) begin if ( reset = '1' ) then count <= ( others => '0' ); direction <= up ; elsif (rising_edge( clock )) then -- Note that assignments to direction and count both produce FFs if ( countEn = '1' ) then case direction is when up => count <= count + "1" ; when down => count <= count - "1" ; end case ; -- Change direction 1 clock early to allow for delayed action on following edge if ( count = "001" ) then direction <= up ; elsif ( count = "110" ) then direction <= down ; end if ; end if ; end if ; end process sync; end architecture Behavioral;

Digital Electronics - Tutorial 40 of 46 Q4) Example VHDL P1: process( reset, clock ) begin if (reset = '1') then x <= '0'; elsif (rising_edge(clock)) then x <= w; end if; end process P1; P2: process( clock ) begin if (rising_edge(clock)) then if (clear = '1') then x <= '0'; else x <= w; end if; end if; end process P2; Asynchronous Reset Synchronous Reset (Clear input)

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Digital Electronics - Tutorial 41 of 46 Q5) Register with 3-state outputs. -------------------------------------------------------------------------------- -- Tutorial 10 Q4) - Loadable register with 3-state output buffer -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164. ALL ; entity Reg is Generic ( width : integer := 8 ); Port ( reset : in std_logic ; clock : in std_logic ; loadEn : in std_logic ; oEn : in std_logic ; d : in std_logic_vector (width-1 downto 0); o : out std_logic_vector (width-1 downto 0) ); end entity Reg; --------------------------------------------------------- -- Implementation using a single process --------------------------------------------------------- architecture allInOne of Reg is signal q : std_logic_vector (width-1 downto 0); begin allOfIt: process (reset, clock, oEn, q) begin -- register portion if (reset = '1') then q <= ( others => '0'); elsif ( rising_edge (clock)) then if (loadEn = '1') then q <= d; end if; end if; -- 3-state buffer portion if (oEn = '0') then o <= q; else o <= ( others => 'Z'); end if ; end process allOfIt; end architecture allInOne;

Digital Electronics - Tutorial 42 of 46 ---------------------------------------------------------------------------- -- Implementation using two processes – slightly more efficient to simulate. ---------------------------------------------------------------------------- architecture twoProc of Reg is signal q : std_logic_vector (width-1 downto 0); begin registr: process (reset, clock) begin if (reset = '1') then q <= ( others => '0'); elsif ( rising_edge (clock)) then if (loadEn = '1') then q <= d; end if; end if; end process registr; buff: process (oEn, q) begin if (oEn = '0') then o <= q; else o <= ( others => 'Z'); end if; end process buff; end architecture twoProc;

Digital Electronics - Tutorial 43 of 46 Q6) a) Fire Coil2 Coil1 100 200 200 200 100 Counter Clear Idle Pulse1 Between Pulse2 Release Idle Idl e pulse1 1 0 between 0 0 Pulse2 0 1 Release 0 0 1XX/1 <state> c1,c2 sw,C100,C200/clear X1X/1 XX1/1 X0X/0 0XX/X XX0/0 XX1/1 XX0/0 0XX/X 1XX/X

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Digital Electronics - Tutorial 44 of 46 b) See attached VHDL files c) The input must be synchronised to the clock before being used in the controller. Sw CNT<=0 Coil1=1 C=100 CNT<=0 C=200 CNT<=0 Coil2=1 C=200 Sw Y Y Y N N N Y N N Y