433HW10allee (1)

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Arizona State University *

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470

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Electrical Engineering

Date

Nov 24, 2024

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pdf

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2

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1 Homework 10 – eee433 NMOS PMOS uCox/2 (uA/V 2 ) 110 50 Vth (V) 0.4 -0.4 Lambda (V -1 ) 0.2 0.2 (for L=0.5um) V dd = 3.3V Vss = 0V CL = 15pF Cc = 5pF All L=0.5um All V eff = 0.2V All devices are saturated. Phi = 0.8V (built in potential of pn junction) Cj = 10 -3 F/m 2 (0 bias capacitance of pn junction for both nmos and pmos) Cgdo = 10 -10 F/m (for both nmos and pmos) D = 0.5um The DC voltage at the output is 2.5V You can assume that CL and Cc are much larger than the other capacitances.
2 Noise a) What is the mean square current noise for M7 from its own drain to source? b) What is the mean square noise voltage for M7 referred to the input of the op-amp? c) Let’s say you are trying to build a receiver on a submarine for an 82Hz signal. Your receiver has noise spectral density given by the following equation. Assume you want to make a measurement every 2 second. ࢔ି࢏࢔࢖࢛࢚ ൌ ૜࢞૚૙ ି૚૞ ૛૛૞࢞૚૙ ష૚૞ ࡴࢠ What is the input referred rms noise if you your amplifier has an intrinsic bandwidth of 1kHz? 1kHz is a ‘brickwall’ bandwidth. d) How much mean square noise voltage does M5 contribute to the output? Hint: If the current in M5 increases, how much does the output voltage change for an ideal op-amp?
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