EEE598_F15_ Exam 1_solution_key

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Arizona State University *

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Course

598

Subject

Electrical Engineering

Date

May 20, 2024

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pdf

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7

Uploaded by CaptainPanther1874

Midterm Exam 1 EEE598 VLSI Analog Filter & Signal Processing Circuits Fall 2015 Arizona State University Instructor: Dr. Hongjiang Song Exam Time: 6:00pm 7:15pm Tuesday, September 29, 2015 Name: _________________ ID#: _________________ General instruction: This is a closed book/notes exam. However, you may bring a sheet (8.5x11) of notes and a calculator to this exam. Good luck! Page 1/7 Solution
Problem 1 (Passive LRC filter, transfer function, Bode plots and steady state response) Shown in circuit below is a normalized (i.e. simplified) filter model of a VLSI high-speed I/O circuit. 1.1) Derive the s-domain transfer function for the filter (10 points). ? ) ( ) ( ) ( s V s V s H A B H(s) = 1/(s^2+0.5s+1.001) Pole ~ -0.25+/j Page 2/7 A B L = 1 C = 1 R = 0.5 C = 1000 Note: there is a typo in sheet. So everyone get 5 points for this question
1.2) Find the zero(s) and pole(s) of the transfer function and plot them in the s-plane below. Sketch the gain and phase responses of the circuit in the graphs given below (15 points). 1.3) For each input signal given below sketch the steady state output V B (t) in the same graph with the input. Please indicate your important values in the output signals (i.e. peak and phase or delay) (15 points) Page 3/7 j s-plane -1 -1 0 0 -2 -2 1 1 Gain (dB) 20 -20 0 180 -180 0 Phase (degree) 10 log 10 log 2 2 V A (t) t (sec.) 1 -1 3.14 0 6.28 t (sec.) 1 -1 0.314 0 0.628 t (sec.) 1 -1 31.4 0 62.8 V A (t) V A (t) 6dB = 10 |H| ~ 0.1 Phase ~ -180 degree = 1 |H| = 2 Phase = -90 degree = 0.1 |H| ~ 1 Phase ~ 0 degree
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