HW8 EC311 (2).

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Jan 9, 2024

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Fall 2023 / EC311 / HW 8 Fall 2023 / EC311 Digital Logic Design Instructor: Prof. Douglas Densmore Homework 8 Due: 11/15 (12:20pm right after class starts) Problem 1 a. Reduce the number of states for the FSM diagram below using an implication chart. Draw the resulting FSM diagram. (10pts) b. Reduce the number of states for the FSM diagram below using the partitioning method (output for the state is in “[]”). Draw the resulting FSM diagram. (10pts)
Problem 2 a. Compare the logic size (number of gate inputs) and the delay (number of gate delays; assume 1 delay unit per gate) of a minimal bitwidth encoding vs. a 3- bit output encoding vs. a 4-bit one-hot encoding for the following FSM. Draw the resulting circuits for all (10pts). b. Compare the logic size (number of gate inputs) and the delay (number of gate delays; assume 1 delay unit per gate) of a minimal bitwidth encoding, an output encoding (if possible; if not explain why), and a one hot encoding of the following FSM. Draw the resulting circuits for all (10pts) Problem 3 a. Create the controller for the following Mealy FSM. Include truth table, use minimal bitwidth encoding, and draw the complete combinational logic circuits. (10pts)
b. Convert the previous Mealy FSM diagram to its nearest Moore FSM equivalent diagram. (5pts) Problem 4 Use a timing diagram containing a clock signal, Q output signal, and D input signal for a D flip flop to show a: (8pts; 2pts each) a. Setup time violation b. Hold time violation c. Synchronous reset with an additional input R d. Asynchronous reset with an additional input AR Discuss how to you would create a circuit to avoid setup time and hold time violations. How and why might you use a flip flop reset? Why would you use an asynchronous versus synchronous reset? (8pts)
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