1 Introductory Concepts 2 Number Systems, Operations, And Codes 3 Logic Gates 4 Boolean Algebra And Logic simplification 5 Combinational Logic Analysis 6 Functions Of Combinational Logic 7 Latches, Flip-flops, And Timers 8 Shift Registers 9 Counters 10 Programmable Logic 11 Data Storage 12 Signal Conversion And Processing 13 Data Transmission 14 Data Processing And Control expand_more
4.1 Boolean Operations And Expressions 4.2 Laws And Rules Of Boolean Algebra 4.3 Demorgan’s Theorems 4.4 Boolean Analysis Of Logic Circuits 4.5 Logic Simplification Using Boolean Algebra 4.6 Standard Forms Of Boolean Expressions 4.7 Boolean Expressions And Truth Tables 4.8 The Karnaugh Map 4.9 Karnaugh Map Sop Minimization 4.10 Karnaugh Map Pos Minimization 4.11 The Quine-mccluskey Method 4.12 Boolean Expressions With Vhdl Chapter Questions expand_more
Problem 1TFQ: Variable, complement, and literal are all terms used in Boolean algebra Problem 2TFQ: Addition in Boolean algebra is equivalent to the OR function. Problem 3TFQ Problem 4TFQ: The commutative law, associative law, and distributive law are all laws in Boolean algebra. Problem 5TFQ Problem 6TFQ: When a Boolean variable is multiplied by its complement, the result is the variable Problem 7TFQ Problem 8TFQ: SOP means series of products Problem 9TFQ: Karnaugh maps can be used to simplify Boolean expressions. Problem 10TFQ: A4-variable Karnaugh map has eight cells. Problem 11TFQ: VHDL is a type of hardware definition language Problem 12TFQ: A VHDL program consists of an entity and an architecture. Problem 1ST Problem 2ST: The Boolean expression A + B + C is a sum term a literal term a product term a complemented term Problem 3ST: The Boolean expression ABCD is a sunn term a product term a literal term always 1 Problem 4ST: The domain of the expression ABCD+AB+CD+B A and D B only A S, C, and D none of these Problem 5ST Problem 6ST Problem 7ST Problem 8ST: Which one of the following is not a valid rule of Boolean algebra? a.A+1=1b.A=Ac.AA=Ad.A+0=A Problem 9ST: Which of the following rules states that if one input of an AND gate is always 1, the output is... Problem 10ST Problem 11ST: The Boolean expression X = AB + CD represents two ORs ANDed together a 4-input AND gate two ANDs... Problem 12ST: An example of a sum-of-products expression is A+B(C+D) AB+AC+ABC (A+B+C)(A+B+C) both answers (a) and... Problem 13ST Problem 14ST: An example of a standard SOP expression is AB+ABC+ABD ABC+ACD AB+AB+AB ABCD+AB+A Problem 15ST Problem 16ST Problem 17ST Problem 18ST: VHDL is a type of programmable logic hardware description language programmable array logical... Problem 19ST: In VHDL, a port is a type of entity a type of architecture an input or output a type of variable Problem 20ST: Using VDHL, a logic circuits inputs and outputs are described in the architecture component entity... Problem 1P: Using Boolean notation, write an expression that is a 1 whenever one or more of its variables (A B,... Problem 2P: Write an expression that is a 1 only if all of its variables (A, 6, C, D, and E) are 1 s. Problem 3P: Write an expression that is a 1 when one or more of its variables (A 6, and C) are Os. Problem 4P Problem 5P Problem 6P Problem 7P Problem 8P: Identify the Boolean rule(s) on which each of the following equalities is based... Problem 9P Problem 10P Problem 11P Problem 12P: Write the Boolean expression for each of the logic gates in Figure 4-56. Problem 13P: Write the Boolean expression for each of the logic circuits in Figure 4-57? Problem 14P: Draw the logic circuit represented by each of the following expressions: A+B+C ABC AB+C AB+CD Problem 15P: Draw the logic circuit represented by each expression: AB+AB AB+AB+ABC AB(C+D) A+B[ C+D(B+C) ] Problem 16P: Draw a logic circuit for the case where the output, ENABLE, is LOW only if the inputs, ASSERT and... Problem 17P: Develop the truth table for each of the circuits in Figure 4-58 Problem 18P: Construct a truth table for each of the following Boolean expressions A+B AB AB+BC (A+B)C (A+B)(B+c) Problem 19P: Using Boolean algebra techniques, simplify the following expressions as much as possible A(A+B)... Problem 20P: Using Boolean algebra, simplify the following expressions (A+B)(A+C) AB+ABC+ABCD+ABCDE AB+ABC+A... Problem 21P Problem 22P: Determine which of the logic circuits in Figure 4-59 are equivalent Problem 23P: Convert the following expressions to sum-of-product (SOP) forms (A+B)(C+B) (A+BC)C (A+C)(AB+AC) Problem 24P Problem 25P: Define the domain of each SOP expression in Problem 23 and convert the expression to standard SOP... Problem 26P Problem 27P Problem 28P Problem 29P Problem 30P Problem 31P Problem 32P Problem 33P: Develop a truth table for each of the SOP expressions: AB+ABC+AC+ABC X+YZ+WZ+XYZ Problem 34P: Develop a truth table for each of the standard POS expressions: (A+B+C)(A+B+C)(A+B+C)... Problem 35P: Develop a truth table for each of the standard POS expressions: (A+B)(A+C)(A+B+C)... Problem 36P: For each truth table in Table 4-15 0, derive a standard SOP and a standard POS expression. Problem 37P Problem 38P Problem 39P Problem 40P Problem 41P Problem 42P: Expand each expression to a standard SOP form: AB+ABC+ABC A+BC ABCD+ACD+BCD+ABCD AB+ABCD+CD+BCD+ABCD Problem 43P Problem 44P Problem 45P Problem 46P: Use the Karnaugh map method to implement the minimum SOP expression for the logic function specified... Problem 47P: Solve Problem 46 for a situation in which the last six binary combinations are not allowed. Problem 48P Problem 49P Problem 50P: For the function specified in Table 4—16, determine the minimum POS expression using a Karnaugh... Problem 51P: Determine the minimum POS expression for the function in Table 4-17. Problem 52P Problem 53P Problem 54P: List the minterms in the expression X=ABCD+ABCD+ABCD+ABCD+ABCD+ABCD Problem 55P: Create a table for the number of 1 s in the minterms for the expression in Problem 54 (similar to... Problem 56P: Create a table of first level minterms for the expression in Problem 54 (similar to Table 4-11) Problem 57P: Create a table of second level minterms for the expression in Problem 54 (similar to Table 4-12). Problem 58P: Create a table of prime implicants for the expression in Problem 54 (similar to Table 4-13). Problem 59P: Determine the final reduced expression for the expression in Problem 54. Problem 60P: Write a VHDL program for the logic circuit in Figure 4-60 Figure 4-60 Problem 61P Problem 62P Problem 63P: Explain the purpose of the invalid code detector. Problem 64P: For segment c, how many fewer gates and inverters does it take to implement the minimum SOP... Problem 65P: Repeat Problem 64 for the logic for segments d through g. Problem 66P: The logic for segments b and c in Figure 4-53 produces LOW outputs to activate the segments. If a... Problem 67P: Redesign the logic for segment a in the Applied Logic to include the letter F in the display. Problem 68P Problem 69P: Design the invalid code detector. Problem 70P: Open file P04-70. For the specified fault, predict the effect on the circuit. Then introduce the... Problem 71P: Open file P04-71. For the specified fault, predict the effect on the circuit. Then introduce the... Problem 72P: Open file P04-72. For the observed behavior indicated, predict the fault in the circuit. Then... format_list_bulleted