Chapter 4, Problem 5RQ

Program Plan Intro

Logic gate:

• Logic gate is an electronic circuit that is used to take logical decisions based on the input.
• It contains one or more number of inputs and one output.
• The working of logic gate is based on the binary principle that has two states either logic 0 or logic 1.
• The output of logic gate is produced when it satisfies any of its logic conditions.
• The logic condition depends upon the type of the gates and the number of inputs.
• The primary logic gates include AND, OR and NOT and the combinations of these gates are used to implement any of the other logic gates.

AND gate:

• The AND gate refers to a logic gate whose output will be HIGH only when all the inputs are HIGH.
• The output of AND gate will be LOW when any one of its input is LOW.
• The symbol to represent AND gate is given below:

• The truth table for AND gate is as follows:

INPUT A	INPUT B	OUTPUT Y
0	0	0
0	1	0
1	0	0
1	1	1

OR gate:

• The OR gate refers to a logic gate whose output will be HIGH when any one of its inputs are HIGH.
• The output of AND gate will be LOW when both the inputs are LOW.
• The symbol to represent OR gate is given below:

• The truth table for OR gate is as follows:

INPUT A	INPUT B	OUTPUT Y
0	0	0
0	1	1
1	0	1
1	1	1

NOT gate:

• The NOT gate refers to a logic gate whose output will be HIGH when it’s input is LOW and whose output will be LOW when it’s input is HIGH.
• The symbol to represent NOT gate is given below:

• The truth table for NOT gate is as follows:

INPUT A	OUTPUT Y
0	1
1	0

Explanation of Solution

b.

Logic gate circuit:

The logic gate circuit for the given relay ladder diagram is as follows.

Explanation:

In the above given logic gate circuit,

• The input “C” is connected to logic NOT gate and the corresponding output will be “$\overline{C}$”.
• Then the inputs “A”, “B”, “$\overline{C}$” are connected to a logic OR gate and the corresponding output will be $(A+B+\overline{C})$.
• Now, the resultant along with the other input “D” is connected to a logic AND gate whose output will be $Y=(A+B+\overline{C})D$