LogixPro PLC Lab Manual for Programmable Logic Controllers
LogixPro PLC Lab Manual for Programmable Logic Controllers
5th Edition
ISBN: 9781259680847
Author: Frank D. Petruzella
Publisher: McGraw-Hill Education
Question
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Chapter 4, Problem 6RQ
Program Plan Intro

Logic gate:

  • Logic gate is an electronic circuit that is used to take logical decisions based on the input.
  • It contains one or more number of inputs and one output.
  • The working of logic gate is based on the binary principle that has two states either logic 0 or logic 1.
  • The output of logic gate is produced when it satisfies any of its logic conditions.
  • The logic condition depends upon the type of the gates and the number of inputs.
  • The primary logic gates include AND, OR and NOT and the combinations of these gates are used to implement any of the other logic gates.

AND gate:

  • The AND gate refers to a logic gate whose output will be HIGH only when all the inputs are HIGH.
  • The output of AND gate will be LOW when any one of its input is LOW.
  • The symbol to represent AND gate is given below:

LogixPro PLC Lab Manual for Programmable Logic Controllers, Chapter 4, Problem 6RQ , additional homework tip  1

  • The truth table for AND gate is as follows:
INPUT AINPUT BOUTPUT Y
000
010
100
111

OR gate:

  • The OR gate refers to a logic gate whose output will be HIGH when any one of its inputs are HIGH.
  • The output of AND gate will be LOW when both the inputs are LOW.
  • The symbol to represent OR gate is given below:

LogixPro PLC Lab Manual for Programmable Logic Controllers, Chapter 4, Problem 6RQ , additional homework tip  2

  • The truth table for OR gate is as follows:
INPUT AINPUT BOUTPUT Y
000
011
101
111

NOT gate:

  • The NOT gate refers to a logic gate whose output will be HIGH when it’s input is LOW and whose output will be LOW when it’s input is HIGH.
  • The symbol to represent NOT gate is given below:

LogixPro PLC Lab Manual for Programmable Logic Controllers, Chapter 4, Problem 6RQ , additional homework tip  3

  • The truth table for NOT gate is as follows:
INPUT AOUTPUT Y
01
10

Explanation of Solution

b.

Logic gate circuit:

The logic gate circuit for the given Boolean expression Y=AB+CD is as follows.

Explanation:

In the above given logic gate circuit,

  • The inputs “A” and “B” are connected to logic AND gate and the corresponding output will be (AB)

Explanation of Solution

c.

Logic gate circuit:

The logic gate circuit for the given Boolean expression Y=(A+B)(C¯+D) is as follows.

Explanation:

In the above given logic gate circuit,

  • The inputs “A” and “B” are connected to logic OR gate and the corresponding output will be (A+B).
  • The input “C” is connected to logic NOT gate and the corresponding output will be “C¯

Explanation of Solution

d.

Logic gate circuit:

The logic gate circuit for the given Boolean expression Y=[A¯(B+CD)] is as follows.

Explanation:

In the above given logic gate circuit,

  • The inputs “C” and “D” are connected to logic AND gate and the corresponding output will be (CD).
  • Now, the resultant along with other input “B” is connected to logic OR gate whose output will be (B+CD)

Explanation of Solution

e.

Logic gate circuit:

The logic gate circuit for the given Boolean expression Y=(A¯B+C) is as follows.

Explanation:

In the above given logic gate circuit,

  • The input “A” is connected to logic NOT gate and the corresponding output will be “A¯

Explanation of Solution

f.

Logic gate circuit:

The logic gate circuit for the given Boolean expression Y=[(ABC+D)EF¯] is as follows.

Explanation:

In the above given logic gate circuit,

  • The inputs “A”, “B” and “C” are connected to logic AND gate and the corresponding output will be (ABC).
  • Now, the resultant along with the other input “D” is connected to logic OR gate whose output will be (ABC+D)

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make corrections of this program based on the errors shown. this is CIS 227 .
Create 6 users: Don, Liz, Shamir, Jose, Kate, and Sal. Create 2 groups: marketing and research. Add Shamir, Jose, and Kate to the marketing group. Add Don, Liz, and Sal to the research group. Create a shared directory for each group. Create two files to put into each directory: spreadsheetJanuary.txt meetingNotes.txt Assign access permissions to the directories:  Groups should have Read+Write access Leave owner permissions as they are  “Everyone else” should not have any access   Submit for grade: Screenshot of  /etc/passwd contents showing your new users Screenshot of /etc/group contents showing new groups with their members Screenshot of shared directories you created with files and permissions
⚫ your circuit diagrams for your basic bricks, such as AND, OR, XOR gates and 1 bit multiplexers, ⚫ your circuit diagrams for your extended full adder, designed in Section 1 and ⚫ your circuit diagrams for your 8-bit arithmetical-logical unit, designed in Section 2. 1 An Extended Full Adder In this Section, we are going to design an extended full adder circuit (EFA). That EFA takes 6 one bit inputs: aj, bj, Cin, Tin, t₁ and to. Depending on the four possible combinations of values on t₁ and to, the EFA produces 3 one bit outputs: sj, Cout and rout. The EFA can be specified in principle by a truth table with 26 = 64 entries and 3 outputs. However, as the EFA ignores certain inputs in certain cases, it is easier to work with the following overview specification, depending only on t₁ and to in the first place: t₁ to Description 00 Output Relationship Ignored Inputs Addition Mode 2 Coutsjaj + bj + Cin, Tout= 0 Tin 0 1 Shift Left Mode Sj = Cin, Cout=bj, rout = 0 rin, aj 10 1 1 Shift Right…
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