Chapter 4, Problem 4.19.4E

Explanation of Solution

Impact of the change that is made:

Before change:

When the registers are read the control unit will decode the instruction that is present.

After change:

The register read and latencies of the control that are performed cannot be overlapped

Since overlap is not supported, the latency of the stage ID will be increased.

This increase could affect the clock cycle time of the processor.

Consider if the stage ID tends to be with longest latency.

Impact of change in the performance:

The impact of the change in the performance could be as shown below:

Cycle time before change:

The cycle time before the change will be 250ps at the stage Mem made during the D-Mem read or write operation.

Cycle time after change:

The cycle time after the change is computed as the sum of the control unit and the registers read and write operation...