Enhanced Discovering Computers 2017 (Shelly Cashman Series) (MindTap Course List)
1st Edition
ISBN: 9781305657458
Author: Misty E. Vermaat, Susan L. Sebok, Steven M. Freund, Mark Frydenberg, Jennifer T. Campbell
Publisher: Cengage Learning
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Question
Chapter 3, Problem 2PS
Program Plan Intro
Automatic Teller Machine (ATM):
- ATM is packet-switched service that can be obtained by corporate number of communications at very high speed.
- ATM is similar to frame relay.
- Frame relay is used for transferring data over fixed lines.
- In an organization, ATM is used to transfer data between two points at high transfer rate.
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Q.1. Architecture performance [10 marks]
Answer
A certain microprocessor requires either 2, 4, or 6 machine cycles to perform various operations.
⚫ (40+g+f)% require 2 machine cycles,
⚫ (30-g) % require 4 machine cycles, and
⚫ (30-f)% require 6 machine cycles.
(a) What is the average number of machine cycles per instruction for this microprocessor?
Answer
(b) What is the clock rate (machine cycles per second) required for this microprocessor to be a
"1000 MIPS" processor?
Answer
(c) Suppose that 35% of the instructions require retrieving an operand from memory which
needs an extra 8 machine cycles. What is the average number of machine cycles per
instruction, including the instructions that fetch operands from memory?
Chapter 3 Solutions
Enhanced Discovering Computers 2017 (Shelly Cashman Series) (MindTap Course List)
Ch. 3 - Prob. 1SGCh. 3 - Prob. 2SGCh. 3 - Prob. 3SGCh. 3 - Prob. 4SGCh. 3 - Prob. 5SGCh. 3 - Prob. 6SGCh. 3 - Prob. 7SGCh. 3 - Prob. 8SGCh. 3 - Prob. 9SGCh. 3 - Prob. 10SG
Ch. 3 - Prob. 11SGCh. 3 - Prob. 12SGCh. 3 - Prob. 13SGCh. 3 - Prob. 14SGCh. 3 - Prob. 15SGCh. 3 - Prob. 16SGCh. 3 - Prob. 17SGCh. 3 - Prob. 18SGCh. 3 - Prob. 19SGCh. 3 - Prob. 20SGCh. 3 - Prob. 21SGCh. 3 - Prob. 22SGCh. 3 - Prob. 23SGCh. 3 - Prob. 24SGCh. 3 - Prob. 25SGCh. 3 - Prob. 26SGCh. 3 - Prob. 27SGCh. 3 - Prob. 28SGCh. 3 - Prob. 29SGCh. 3 - Prob. 30SGCh. 3 - Prob. 31SGCh. 3 - Prob. 32SGCh. 3 - Prob. 33SGCh. 3 - Prob. 34SGCh. 3 - Prob. 35SGCh. 3 - Prob. 36SGCh. 3 - Prob. 37SGCh. 3 - Prob. 38SGCh. 3 - Prob. 39SGCh. 3 - Prob. 40SGCh. 3 - Prob. 41SGCh. 3 - Prob. 42SGCh. 3 - Prob. 43SGCh. 3 - Prob. 44SGCh. 3 - Prob. 45SGCh. 3 - Prob. 46SGCh. 3 - Prob. 47SGCh. 3 - Prob. 48SGCh. 3 - Prob. 49SGCh. 3 - Prob. 1TFCh. 3 - Prob. 2TFCh. 3 - Prob. 3TFCh. 3 - Prob. 4TFCh. 3 - Prob. 5TFCh. 3 - Prob. 6TFCh. 3 - Prob. 7TFCh. 3 - Prob. 8TFCh. 3 - Prob. 9TFCh. 3 - Prob. 10TFCh. 3 - Prob. 11TFCh. 3 - Prob. 12TFCh. 3 - Prob. 1MCCh. 3 - Prob. 2MCCh. 3 - Prob. 3MCCh. 3 - Prob. 4MCCh. 3 - Prob. 5MCCh. 3 - Prob. 6MCCh. 3 - Prob. 7MCCh. 3 - Prob. 8MCCh. 3 - Prob. 1MCh. 3 - Prob. 2MCh. 3 - Prob. 3MCh. 3 - Prob. 4MCh. 3 - Prob. 5MCh. 3 - Prob. 6MCh. 3 - Prob. 7MCh. 3 - Prob. 8MCh. 3 - Prob. 9MCh. 3 - Prob. 10MCh. 3 - Prob. 2CTCh. 3 - Prob. 3CTCh. 3 - Prob. 4CTCh. 3 - Prob. 5CTCh. 3 - Prob. 6CTCh. 3 - Prob. 7CTCh. 3 - Prob. 8CTCh. 3 - Prob. 9CTCh. 3 - Prob. 10CTCh. 3 - Prob. 11CTCh. 3 - Prob. 12CTCh. 3 - Prob. 13CTCh. 3 - Prob. 14CTCh. 3 - Prob. 15CTCh. 3 - Prob. 16CTCh. 3 - Prob. 17CTCh. 3 - Prob. 18CTCh. 3 - Prob. 19CTCh. 3 - Prob. 20CTCh. 3 - Prob. 21CTCh. 3 - Prob. 22CTCh. 3 - Prob. 23CTCh. 3 - Prob. 24CTCh. 3 - Prob. 25CTCh. 3 - Prob. 26CTCh. 3 - Prob. 27CTCh. 3 - Prob. 28CTCh. 3 - Prob. 29CTCh. 3 - Prob. 30CTCh. 3 - Prob. 1PSCh. 3 - Prob. 2PSCh. 3 - Prob. 3PSCh. 3 - Prob. 4PSCh. 3 - Prob. 5PSCh. 3 - Prob. 6PSCh. 3 - Prob. 7PSCh. 3 - Prob. 8PSCh. 3 - Prob. 9PSCh. 3 - Prob. 10PSCh. 3 - Prob. 11PSCh. 3 - Prob. 1.1ECh. 3 - Prob. 1.2ECh. 3 - Prob. 2.1ECh. 3 - Prob. 2.2ECh. 3 - Prob. 2.3ECh. 3 - Prob. 3.1ECh. 3 - Prob. 3.2ECh. 3 - Prob. 3.3ECh. 3 - Prob. 4.1ECh. 3 - Prob. 4.2ECh. 3 - Prob. 4.3ECh. 3 - Prob. 5.1ECh. 3 - Prob. 5.2ECh. 3 - Prob. 5.3ECh. 3 - Prob. 1IRCh. 3 - Prob. 2IRCh. 3 - Prob. 3IRCh. 3 - Prob. 4IRCh. 3 - Prob. 1CTQCh. 3 - Prob. 2CTQCh. 3 - Prob. 3CTQCh. 3 - Prob. 4CTQ
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- Q.2. Architecture performance [25 marks] Consider two different implementations, M1 and M2, of the same instruction set. M1 has a clock rate of 2 GHz and M2 has a clock rate of 3.3 GHz. There are two classes of instructions with the following CPIs: Class A CPI for M1 CPI for M2 2.f 1.g B 5 3 C 6 4 Note that the dots in 2 fand 1.g indicate decimal points and not multiplication. a) What are the peak MIPS performances for both machines? b) Which implementation is faster, if half the instructions executed in a certain program are from class A, while the rest are divided equally among classes B and C. c) What speedup factor for the execution of class-A instructions would lead to 20% overall speedup? d) What is the maximum possible speedup that can be achieved by only improving the execution of class-A instructions? Explain why. e) What is the clock rate required for microprocessor M1 to be a "1000 MIPS" (not peak MIPS) processor?arrow_forwardPLEASE SOLVE STEP BY STEP WITHOUT ARTIFICIAL INTELLIGENCE OR CHATGPT I don't understand why you use chatgpt, if I wanted to I would do it myself, I need to learn from you, not from being a d amn robot. SOLVE STEP BY STEP I WANT THE DIAGRAM PERFECTLY IN SIMULINKarrow_forwardI need to develop and run a program that prompts the user to enter a positive integer n, and then calculate the value of n factorial n! = multiplication of all integers between 1 and n, and print the value n! on the screen. This is for C*.arrow_forward
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