ELECTRICAL WIRING:RESIDENTAL-6 PLANS
18th Edition
ISBN: 9781305098329
Author: MULLIN
Publisher: CENGAGE L
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Chapter 10, Problem 6R
What color are the faceplates in the bathrooms? Refer to the specifications. ________________
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illustrate the phenomenon of phase reversal in CE amplifier
i- When signal current =OA, so IB-8uA
ii- When input signal reaches positive peak, so IB=16uA
ii- When input signal reaches negative peak, so IB=4uA
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Rc=6kn
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8 μA
4 μА
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RE
ẞ = 100
VC
In the circuit shown, find the voltage gain. Given that ẞ = 80 and input resistance Rin=2kQ.
SIGNAL
+10 V
Rc=6kn
4-2
210
For the transistor amplifier shown, R₁-11kQ, R2=6kQ, Rc=2kQ, RE-3kQ and R₁=2k0.
(i) Draw d.c. load line
(ii) Determine the DC operating point
(iii) Draw a.c. load line. Assume V_BE = 0.7 V. and determine the new operating point
+ Vcc = 15 V
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Chapter 10 Solutions
ELECTRICAL WIRING:RESIDENTAL-6 PLANS
Ch. 10 - Prob. 1RCh. 10 - There is a 3-way switch in the bedroom hallway...Ch. 10 - What wattage was used for each vanity luminaire to...Ch. 10 - What is the current draw for the answer given in...Ch. 10 - Exposed non-current-carrying metallic parts of...Ch. 10 - What color are the faceplates in the bathrooms?...Ch. 10 - Prob. 7RCh. 10 - a. The NEC in Section _______________ requires...Ch. 10 - Hanging luminaires must be kept at least...Ch. 10 - The following is a layout of a lighting circuit...
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- the first part is the second part write your answer such as: (AND, OR, INVERTER, NAND, NOR) D₁ AK D, R₁ B K First Part? the third part is , and the total are R4 R7 Output R5 R₁ T R6 R3 -UBB Second Part? Third Part? Total?arrow_forwardA multistage amplifier has six stages each of which has a power gain of 40. what is the - Total gain of the amplifier in db ? ii- If the negative feedback of 15db is employed, find the resultant gainarrow_forward9.36 Consider the finite-state machine logic implementation in Figure P9.36. (a) Determine the next-state and output logic expressions. (b) Determine the number of possible states. J1 Clk K₁ 101 Ут J2 Clk K₂ Clk Figure P9.36 0 y2 10arrow_forward
- 9.34 Consider the finite-state machine logic implementation in Figure P9.34. (a) Determine the next-state and output logic expressions. (b) Determine the number of possible states. (c) Construct a state assigned table. (d) Construct a state table. (e) Construct a state diagram. (f) Determine the function of the finite-state machine. T₁ x Clk Figure P9.34 Q Clk Q الا T₂ Q 32 Clk Q T3 Q Clk Q Узarrow_forward9.35 Consider the finite-state machine logic implementation in Figure P9.35. (a) Determine the next-state and output logic expressions. (b) Determine the number of possible states. (c) Construct a state assigned table. (d) Construct a state table. (e) Construct a state diagram. (f) Determine the function of the finite-state machine. Clk J Clk K₁ 10 Ут J2 Clk K₂ 10 32 Figure P9.35arrow_forward9.56 Using JK flip-flops, design a synchronous counter that counts in the sequence 1, 3, 0, 2, 1, ... The counter counts only when its enable input x is equal to 1; otherwise, the counter is idle.arrow_forward
- 9.65 Using T flip-flops, design a synchronous counter that counts in the sequence 0, 2, 4, 6, 0, ... The counter counts only when its enable input x is equal to 1; otherwise, the counter is idle.arrow_forward2 Using D flip-flops, design a synchronous counter that counts in the sequence 1, 4, 7, 1, The counter counts only when its enable input x is equal to 1; otherwise, the counter is idle.arrow_forwardQ1: Write a VHDL code to implement the finite state machine described in the state diagram shown below. Clk D 0 CIK Q D 0 Cik Q =arrow_forward
- Q1: Consider the finite state machine logic implementation in Fig. shown below: Construct the state diagram. Repeat the circuit design using j-k flip flop. r" Clk Y D' Y, Clk Q D Clk 10 0 22 3'2arrow_forwardQ: Write a VHDL code to implement the finite state machine described in the state diagram shown below. T 2 Clk Q Clk T₂ 0 la Clk T3 Q Cik 0arrow_forwardDo you happen to know what is the complete circuit?arrow_forward
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