You're now incorporating a Memory Management Unit so your processor can support Virtual Memory. Assuming "PTE_base_addr" is defined as a 16 bits register, "current_PTE" is defined as a 16 bits register, and "virt_addr" is defined as an input, fill in the following Verilog code for implementing the PTE address and the final physical address, assuming a 16 bit address space and 256-bytes pages. wire [] pte_addr = wire [] phys_addr = %3D

You're now incorporating a Memory Management Unit so your processor can support Virtual Memory. Assuming "PTE_base_addr" is defined as a 16 bits register, "current_PTE" is defined as a 16 bits register, and "virt_addr" is defined as an input, fill in the following Verilog code for implementing the PTE address and the final physical address, assuming a 16 bit address space and 256-bytes pages. wire [] pte_addr = wire [] phys_addr = %3D

Name: You're now incorporating a Memory Management Unit so your processor c
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Description: You're now incorporating a Memory Management Unit so your processor cansupport Virtual Memory. Assuming "PTE_base_addr" is defined as a 16 bits register,"current_PTE" is defined as a 16 bits register, and "virt_addr" is defined as an input,fill in t

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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1. 6502 assembly language references data in memory locations using an operand value containing the address (without the # character that indicates an immediate value). For example, the LDA $00 instruction loads the byte at memory address $00 into A. STA $01 stores the byte in A into address $01. Addresses can be any value in the range 0 to SFFFF, assuming memory exists at the address and the address is not already in use for some other purpose. Using your preferred 6502 emulator, write 6502 assembly code to store a 16-bit value into addresses $00-$01, store a second value into addresses $02-$03, then add the two values and store the result in $04-$05. Be sure to propagate any carry between the two bytes. Ignore any carry from the 16-bit result. Test with $0000+$0001, $00FF+$0001, and $1234+$5678.
For each question, give the following three values for the last line of each code block following the execution of the entire block: 1. the memory address which that line writes to, 2. the value that is written to that address, and 3. the number of distinct memory reads required by that line. If you cannot determine the memory address from the information given, enter 0 for the address. When computing the number of memory reads, assume nothing about the value of registers prior to the execution of the last statement: count a read even if the previous line also read (or wrote) the location. Count the number of distinct memory locations read by that statement; that is, if the line reads a memory location multiple times, count it only once. Assume that memory accesses always succeed, i.e. that all memory addresses are accessible to the program. For example, for the following code block: int *foo (int *)0x1000; int *bar = (int *)0x1000; *foo = 1; *foo=foo + *bar + 1; you would answer…
Giventhe following assignment of some program’s virtual pages to physical pages in a system with 4 KiB byte pages, what physical memory address corresponds to virtual address 20000? (All values are given in decimal.)
A user program before being executed goes through several steps. Binding of symbolic addresses to relocatable addresses happens along the way. Discuss the different ways in which these binding/ mapping of instructions and data to memory addresses can happen.
I have this problem from my textbook that I do not understand, despite re-reading the section on segmentation and paging. "The IBM system/370 architecture uses a two-level memory structure and refers to the two levels as segments and pages, although the segmentation approach lacks many of the features described in Chapter 8. For the basic 370 architecture, the page size may be either 2 KB or 4 KB, and the segment size is fixed at either 64 KB or 1 MB. For the 370/XA and 370/ESA architectures, the page size is 4 KB and the segment size is 1 MB. What advantages of segmentation does this scheme lack? What is the benefit of segmentation for the 370?"Can you help me undertand what they are looking for in this explanation?
In lab this week you wrote code that simulates a simple computer; that code could be turned into a circuit. Assume that we have set up the following: • an 8-bit pc register, with 8-bit input pc_in and 8-bit output pc_out. • memory returns the instruction on the 8-bit output code_byte. Your code used a get_bits function we provided to retrieve a 2-bit part of the instruction (code_byte) as the index into the register file for register A. In a physical chip, the simplest correct form of the 2-bit extraction would be to: A. Connect 2 of the 8 wires that make up the code_byte to the register file as needed (no gates) B. A right-shift circuit to move the 2 bits for A to the least significant bits and use those two wires C. A mux with 8 bits of the code_byte as inputs and the 2 bits we want as the selector D. An even larger circuit than the ones above
Our ‘mostly 8-bit’ design has the problem that computed pointers can only range over256 bytes of memory. This makes using the screen difficult (though not impossible!). Howmight you extend the instruction set to make this easier? [Hint: think about spare bits inthe C-instruction.]
3. The table below represents a stack stored in a contiguous block of memory cells (as discussed in the text). If the base of the stack is at address 0x10 and the stack pointer contains the value 0x12, what value is retrieved by a pop instruction? What value is in the stack pointer after the pop operation? Address 0x10 0x11 0x12 0x13 0x14 Contents 'F' 'C' 'A' 'B' 'E'
Suppose a computer using direct mapped cache has 224 bytes of byte- addressable main memory and a cache size of 64K bytes, and each cache block contains 32 bytes. (Note: 64K = 26 * 210) a) How many blocks of main memory are there? b) What is the format of a memory address as seen by cache, i.e., what are the sizes of the tag, block, and offset fields?
Before we can store (save) or retrieve (load) data in and out of the main memory, we need to provide the memory address to the memory control unit. This address uniquely identifies one single location (word or record) of the memory. Suppose this address is placed in Memory Address Register (MAR) prior to each memory access. What is the size of MAR for a 4GB RAM? (RAM is byte- addressable and each word is 2 bytes). Show all the work.
We want to build a word organized main memory of 8 GB for a 32-bit CPU architecture composed of word organized memory modules of 30-bit address and 8-bit data buses each. a) Draw the interface of the main memory by clearly indicating the widths of the buses. b) Howmanymemorymoduleswouldbenecessarytobuildthememorysystem? c) Design the main memory internal organization built out of the above memory modules (use multiplexers and/or decoders as needed) by clearly indicating the widths of the used busses d) CanweusethismemorysystemasRAMfortheCPUinProblem1?Explainyouranswer.
Write instructions, starting at address 100H in program memory, to store the data 65H into 40 (decimal value) consecutive memory locations starting from the address AOH in data memory. In this task, indirect addressing mode should be used. Otherwise, no credit will be given.