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You need to show the calculation in detail. If you make any assumptions to solve this problem, please clarify that in your answer. Assume a 5-stage pipelined CPU (IF – ID - MU- EX-WR) requires following time for different sections: Pipeline stages Fetch Unit Decode Unit Memory Unit Required time 15 ns 10 ns 18 ns. Execution Unit 7 ns Write back Unit 15 ns The maximum delay required to transfer contents from one state to another is 2ns. a. Find the exact clock frequency required to synchronize all pipeline stages b. If a program contains 2 x 106 instructions, calculate the execution time c. Calculate the speedup of this pipelined processor compared to a non-pipelined processor that uses the same clock frequency (you designed in (a)) and requires 10 clock cycles to process each instruction

You need to show the calculation in detail. If you make any assumptions to solve this problem, please clarify that in your answer. Assume a 5-stage pipelined CPU (IF – ID - MU- EX-WR) requires following time for different sections: Pipeline stages Fetch Unit Decode Unit Memory Unit Required time 15 ns 10 ns 18 ns. Execution Unit 7 ns Write back Unit 15 ns The maximum delay required to transfer contents from one state to another is 2ns. a. Find the exact clock frequency required to synchronize all pipeline stages b. If a program contains 2 x 106 instructions, calculate the execution time c. Calculate the speedup of this pipelined processor compared to a non-pipelined processor that uses the same clock frequency (you designed in (a)) and requires 10 clock cycles to process each instruction

Introductory Circuit Analysis (13th Edition)
Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
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You need to show the calculation in detail. If you make any assumptions to solve this problem, please clarify that in your answer. Assume a 5-stage pipelined CPU (IF – ID – MU, EX – WR) requires following time for different sections: Pipeline stages Fetch Unit Required time 15 ns Decode Unit 10 ns Memory Unit Execution Unit 18 ns 7 ns Write back Unit 15 ns The maximum delay required to transfer contents from one state to another is 2ns. a. Find the exact clock frequency required to synchronize all pipeline stages b. If a program contains 2 x 106 instructions, calculate the execution time c. Calculate the speedup of this pipelined processor compared to a non-pipelined processor that uses the same clock frequency (you designed in (a)) and requires 10 clock cycles to process each instruction d. If cache memory is used with the pipelined and non-pipelined processors, which processor will perform better and why? Discuss the relative performances of both the processors with cache. Also discuss the challenges to implement that.
Transcribed Image Text:You need to show the calculation in detail. If you make any assumptions to solve this problem, please clarify that in your answer. Assume a 5-stage pipelined CPU (IF – ID – MU, EX – WR) requires following time for different sections: Pipeline stages Fetch Unit Required time 15 ns Decode Unit 10 ns Memory Unit Execution Unit 18 ns 7 ns Write back Unit 15 ns The maximum delay required to transfer contents from one state to another is 2ns. a. Find the exact clock frequency required to synchronize all pipeline stages b. If a program contains 2 x 106 instructions, calculate the execution time c. Calculate the speedup of this pipelined processor compared to a non-pipelined processor that uses the same clock frequency (you designed in (a)) and requires 10 clock cycles to process each instruction d. If cache memory is used with the pipelined and non-pipelined processors, which processor will perform better and why? Discuss the relative performances of both the processors with cache. Also discuss the challenges to implement that.
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