Which of the following is the output of the above verilog code? Your answer: str=CMP 2007 O str= MP 2007 O CMP 2007 MP 2007

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Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
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Electrical Engineering
Question 7
module TEST_gate;
reg[8*7:1] str;
initial begin
str="CMP 2007";
$display ("str= %s",str);
end
endmodule
Which of the following is the output of the above verilog code?
Your answer:
O str=CMP 2007
O str= MP 2007
O CMP 2007
O MP 2007
Which of the following is the output of the
above verilog code?
Transcribed Image Text:Electrical Engineering Question 7 module TEST_gate; reg[8*7:1] str; initial begin str="CMP 2007"; $display ("str= %s",str); end endmodule Which of the following is the output of the above verilog code? Your answer: O str=CMP 2007 O str= MP 2007 O CMP 2007 O MP 2007 Which of the following is the output of the above verilog code?
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