What would be the clock period to correctly execute the two instructions on the above single-cycle processor? Assume that PC register doesn't take any latency (i.e. Propagating a new PC value to I-Cache/I-Mem doesn’t take any cycle).

Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
Problem 1PE
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Assume that core components of single-cycle processor (shown below) have the following
latencies:
Regs Rd/Wr
80ps/60ps
Adder
Sign-Extend
20ps
I-Mem
Mux
ALU
D-Mem
Shift-Left-2
40ps
50ps
20ps
100ps
200ps
20ps
Single-cycle processor data path:
Left
[25-0
[31-26]
PC+4 [31-28
Shift
Let
[25-21]
Read
Reg. 1
CLK -
(20-16]
Read
Reg. 2
Addr.
Data
Read
15-11
Write
Zero
data
-Cache / -MEM
Res.
Addr.
Read
Wite
Data
data 2
Read
Data
Register File
Write
Data
RegWrite
RegDst
Branch
(15-0)
Sign
Extend
D-Cache
D-Mem
ALU
32
control
ALUSrc
Control InstType
Memwrite
MemtoReg
MemRead
Jump
Suppose that this data path executes only two types of instruction:
sub $rd, $rs, $rt
lw
$rt, offset ($rs)
What would be the clock period to correctly execute the two instructions on the above
single-cycle processor? Assume that PC register doesn't take any latency (i.e.
Propagating a new PC value to I-Cache/I-Mem doesn't take any cycle).
Transcribed Image Text:Assume that core components of single-cycle processor (shown below) have the following latencies: Regs Rd/Wr 80ps/60ps Adder Sign-Extend 20ps I-Mem Mux ALU D-Mem Shift-Left-2 40ps 50ps 20ps 100ps 200ps 20ps Single-cycle processor data path: Left [25-0 [31-26] PC+4 [31-28 Shift Let [25-21] Read Reg. 1 CLK - (20-16] Read Reg. 2 Addr. Data Read 15-11 Write Zero data -Cache / -MEM Res. Addr. Read Wite Data data 2 Read Data Register File Write Data RegWrite RegDst Branch (15-0) Sign Extend D-Cache D-Mem ALU 32 control ALUSrc Control InstType Memwrite MemtoReg MemRead Jump Suppose that this data path executes only two types of instruction: sub $rd, $rs, $rt lw $rt, offset ($rs) What would be the clock period to correctly execute the two instructions on the above single-cycle processor? Assume that PC register doesn't take any latency (i.e. Propagating a new PC value to I-Cache/I-Mem doesn't take any cycle).
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