The truth table below represents a FSM with a l-bit input (x) and a 1-bit output (y). A- Draw the state diagram? B- Is it Mealy or Moor model and why? C- Suppose the

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2: The truth table below represents a FSM with a 1-bit input (x) and a 1-bit output (y).
A- Draw the state diagram?
B- Is it Mealy or Moor model and why?
C- Suppose the machine is initialized to its starting state '00' and then processes the input
values: 1,0,0,1,0,0 (1 input bit after each Clk). What sequence of outputs does it
produce, the state transitions, and what is its final state?
D- Design the logic circuit of this FSM using JK flip flop?
Next State
Output
Present
State
x -1
x -1
A
B.
B.
= AB+C
0.
1.
1.
JA Ja
1.
1
1.
Transcribed Image Text:2: The truth table below represents a FSM with a 1-bit input (x) and a 1-bit output (y). A- Draw the state diagram? B- Is it Mealy or Moor model and why? C- Suppose the machine is initialized to its starting state '00' and then processes the input values: 1,0,0,1,0,0 (1 input bit after each Clk). What sequence of outputs does it produce, the state transitions, and what is its final state? D- Design the logic circuit of this FSM using JK flip flop? Next State Output Present State x -1 x -1 A B. B. = AB+C 0. 1. 1. JA Ja 1. 1 1.
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