Suppose the state of the RAM is as follows and the adjacent assembly code will execute: RAM 0 3 1 @5 1 2 2 A=M 2 0 A=A+1 3 6 4 A=A+1 4 5 5 D=M 10 5 1 6 A=A+1 6 4 7 M=D
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- write a program (XOR.asm) in HACK assembly that implements an XOR function between two 16-bit values stored in RAM[3] and RAM[4] and stores the result in RAM[5]Suppose that the following instructions are found at the given locations in memory: 20 LDA 50 21 BRP 22 22 STO 51 50 100 51 100 Choose the contents of the registers: PC, MAR, MDR, IR, A at the end of fetch-execute cycle for instruction 22: PC MAR MDR IR AEvaluate the effect of the instruction LDR r5, [r7, #4], given the initial values below. Give the final values of all the registers. Registers: r5 = 100 r6 = 1000 r7 = 996 Memory Address Value 992 30 996 40 1000 50 1004 60 1008 70 O r5=50, r6=1000, r7=1000 O r5=40, r6=1000, r7=996 O r5=40, r6=1000, r7=1000 O r5=50, r6=1000, r7=996
- Assume that a memory is initialised as follows: Memory Address Cell Contents 0x000336 0x38 0x000337 0x26 0x000338 0x48 0x000339 0x38 0x00C33A 0x00C33B 0x77 0x38 The following sequence of operations is executed in the given memory: Write(0x00C337, 0x0205) Write (0x00C339, 0x0106) Write(0x00C338, 0x0109) Assume that the read and write operations are done in groups of two bytes, and the system is a big endian system. What is the result of read(0x00C337) +read (0x00C338)? Write your answer in Base 10 (decimal)A computer with a 32-bit 3.5 gigahertz scalar non- pipelined CPU needs to invert the colors of a 150 KB bitmap image file located in the RAM. To do this, each bit of the image must be complemented (Os are converted to 1s and vice-versa). Assume every instruction undergoes the following stages and each stage uses one CPU clock cycle: • Fetch • Decode • Read from memory • Execute • Write to memory Instructions: For this assignment, you must calculate how much time the computer will need to invert the image with a single-core and a dual core CPU. Show and explain your calculations and assumptions in a short paper and answer the following questions: • Will there be any parallel slowdown? Why or why not? Length: 2-3 page explanatory paperGiven a 256x 8 RAM chip, you are asked to build a memory with capacity of 2048 words with a word size equal 16 bits.a. How many 256×8 RAM chips are needed to provide a memory capacity of 2048 words?Specify the layout of the chips by stating the number of rows and columns.b. How many address bits are needed for the built memory?c. How many RAM chips are there per memory word?
- Write the following sequence of code into RISC-V assembler. Assume that x, y, and z are stored in registers x18, x19, and x20 respectively. x = y + 2; z = x – z - 2;Suppose the state of the RAM is as follows and the adjacent assembly code will execute: RAM 0 3 1 2 2 0 فيا 3 6 456 5 1 4 1234567 $1 A = M A = M A = M D = M @4 M = D What will be the value of the RAM[4] following the assembly code execution?Question 2: Write the MIPS code for the given Hexadecimal Machine Code that starts at memory address 0x40000. Line1: 0x0080082A Line2: 0x14200002 Line3: 0x2084FFFF Line4: 0x08010005 Line5: 0x20840001 Line6: 0x1480FFFA Line7: 0x03E00008 Line8: 0x0C010000
- Registers in RISC-V are 64-bit. For the sake of simplicity, consider the following instructions operating on 32-bit registers. Assume that registers x5 and x6 hold the values 0xBBBBBBBB and 0x00000000, respectively. What is the value in x6 for the followingslli x6, x5, 6 Using the result from the part above, what is the value in x6 for the following instruction. srli x6, x6, 6Design a Read Only Memory (ROM) to implement the following, A097803, polynomial A=3(2x2 +1), with input (x): 0≤(x)≤7 (a) What is the size of the initial (unsimplified) ROM ? (b) What is the size of the final (simplified) ROM ? (c) Show in detail the final ROM layout, using LogiSim.Suppose we have the instruction Load 0000. Given memory and register R1 contain thevalues below:R130Memory Address Content0000 40...0010 30...0020 78...0030 55...0040 77...0050 84 Assuming R1 is implied in the indexed addressing mode, determine the actual value loaded into the accumulator using the following addressing modes: a. Immediateb. Directc. Indirectd. Indexed