Draw the truth table and logic diagram for a 4-input priority encoder.   Draw the block diagram for a BCD adder with correction logic.

Q3. Write the difference between and draw the block diagram of the following:-• Half Adder and Half subtractor • Full Adder and Full Subtractor.• Encoder and Decoder• Multiplexer and Demultiplexer• Comparator and EX-NOR gate

Design a sequence detector circuit using the mealy model to detect when a value is not BCD, for example, when 1111 is generated, it must detect that it is not a BCD value.

Simplity the expressions and implement it with two-level NAND gate cicuits: F = BD + BCD '+ AB'C 'D'

Design a 4x2 high priority encoder. By Converting gate by gate,  transform the logic ckts into a MOSFERT circuits.

2- Given a BCD decade counter, show the decoding logic required to decode each of the following state and how it should be connected to the counter. A HIGH output indication is required for each decoded state. MSB is to the left. (a) 0110 (b) 0111 (c) 1000

Design a Moore sequence recognizer that detects the Non-Overlapping sequence “101”. Use binary encoded state labels and design and draw the circuit schematic. (i.e. FSD, Next state generator Table (shows transition from current state to next state), Output Generator Table and schematic circuit. Please use output label as Y and input label as A. Your inputs to D flip-flops will be Data-0 and Data-1, respectfully.

Draw a NAND gate implementation for F=AB+CD   Draw the circuit diagram of a 3-bit even-parity generator using XOR gates.

Draw the block diagram of a four-bit adder-subtractor circuit   Draw the truth table for a four-bit adder with inputs AAA, BBB, carry-in, and outputs sum and carry-out.

Design a Mod-16 synchronous counter.a. Reduce every FF input to its minimal/simplest expression using Karnaugh maps.b. Sketch the resulting circuit.