Draw the truth table and logic diagram for a 4-input priority encoder.   Draw the block diagram for a BCD adder with correction logic.

Q3. Write the difference between and draw the block diagram of the following:-• Half Adder and Half subtractor • Full Adder and Full Subtractor.• Encoder and Decoder• Multiplexer and Demultiplexer• Comparator and EX-NOR gate

Design a sequence detector circuit using the mealy model to detect when a value is not BCD, for example, when 1111 is generated, it must detect that it is not a BCD value.

Design a logic ect to convert Ex-s code to BCD Code

Design a 3-bit comparator and write Verilog code using gate level modeling. Write a Verilog test bench for the above Comparator design.

Simplity the expressions and implement it with two-level NAND gate cicuits: F = BD + BCD '+ AB'C 'D'

Design a 4x2 high priority encoder. By Converting gate by gate,  transform the logic ckts into a MOSFERT circuits.

Design a truth table for a combinational circuit that detects an error in the representation of a decimal digit encoded in BCD. (This circuit should output a 1 when the input is one of the six unused combinations for BCD code.)

Draw the logic diagram of a 2-to-4-line decoder using (a) NOR gates only and (b) NAND gates only. Include an enable input. Invertors are allowed.

"Design a combinational circuit defined by the Boolean function F(X,Y,Z) = (X'+Y)(X'+Z')(X'+Y'+Z), using a decoder and external gate/s. In order to implement this, the size of the decoder should be  and we need to include and external  gate."