Subject: Computer Architecture Question No 1: Dynamic RAM needs to refresh itself after some interval of time to perform smoothly and maintain performance. This is the key difference between dynamic and static RAM. Problem: You are required to discuss this refreshing mechanism in dynamic RAM in detail
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Subject: Computer Architecture
Question No 1:
Dynamic RAM needs to refresh itself after some interval of time to perform smoothly and maintain performance. This is the key difference between dynamic and static RAM.
Problem:
You are required to discuss this refreshing
Step by step
Solved in 2 steps
- b) Machine cycle defines a loop process with four major components. Explain why machine cycle is important? If the components of machine cycle are inter-swapped, would that cause any problems? Can we add another module to rectify the problem caused by inter-swapping? c) Cache memory and RAM both are based on transistor based then why cache memory is needed if we already have RAM (Random Access Memory) as a volatile memory? Is it possible to deploy any one type of memory in computer for all purposes?Create a Synchronous RAM with the following block diagram given below: Where• In_clk : timing for data to be written• write : write control signal• Data_in : 8 bit data to be stored• Address : 4 bit address location• Out_clk : timing for data to be read• read : read control signal• Data_out : 8 bit data to be read Question Simulate the RAM using the following timing parameters:End time : 1.0 msGrid size : 50.0 usIn_clk : count every 5.0 usOut_clk : count every 20.0 us From the simulate please, • Generate and simulate the VHDL codes in Altera Quartus II.• Observe and provide your observation and conclusion.Select the WRONG statement relating to the properties of DRAM memories. (Select the WRONG statement; the statements not selected should be true) The bit line is kept at a voltage between high voltage and ground, during a WRITE operation. A DRAM row-read takes a long time, but once a row is read into a buffer, multiple back-to- back reads to the same row are much faster. Unlike SRAM reads, DRAM reads are "destructive". Memory locations not accessed for some time need to be refreshed periodically.
- There are many parameters that could be used to describe disk performance; among them are: number of bits per track disk capacity (in bits) number of disk surfaces rotational speed rotational latency transfer rate tracks per surface sectors per track blocks per track sectors per block seek time speed of disk arm block-read time number of blocks Some of these parameters are independent, and others are (approximately) linearly related. That is, doubling one doubles the other. Decide which of these parameters are linearly related. Then, select from the list below, the relationship that is true, to within a close approximation. Note: none of the statements may be true exactly, but one will always be much closer to the truth than the other three. Also note: you should assume all dimensions and parameters of the disk are unchanged except for the ones mentioned. a) If you double the number of sectors per block, then you double the number of blocks on the disk. b)…There are many parameters that could be used to describe disk performance; among them are: number of bits per track disk capacity (in bits) number of disk surfaces rotational speed rotational latency transfer rate tracks per surface sectors per track blocks per track sectors per block seek time speed of disk arm block-read time number of blocks Some of these parameters are independent, and others are (approximately) linearly related. That is, doubling one doubles the other. Decide which of these parameters are linearly related. Then, select from the list below, the relationship that is true, to within a close approximation. Note: none of the statements may be true exactly, but one will always be much closer to the truth than the other three. Also note: you should assume all dimensions and parameters of the disk are unchanged except for the ones mentioned. a) If you divide tracks into half as many blocks, then you double the read time for a block.…4. A particular piece of loop iteration requires 6 registers, 2 of which are used to track array indices / loop counters. The other 4 registers are used to hold load values, compute results and store results. If the architecture has 32 general-purpose registers, then how many times can the loop be unrolled by the compiler?
- 3. Consider a memory management unit that uses segmentation with:The use of transistors in the construction of RAM and ROM leads me to believe that there is no need for cache memory.The term "temporary storage" may also be thought of as "random access memory" (RAM) that is momentarily vacant. Imagine a machine that only had one kind of memory—is it even possible?Figure 1 shows the design of a 6116 static CMOS RAM that can store 2K bytes of data. The memory has 16384 cells, arranged as a 128X128 memory matrix. The 11 address lines, which are needed to address 211 bytes of data, are divided into two groups. Lines A10 through A4 select one of the 128 rows in the matrix. Lines A3 through A0 select 8 columns in the matrix at a time since there are 8 data lines. The data outputs from the matrix go through tri-state buffers before connecting to the data I/O lines. These buffers are disabled except when reading from the memory. Table 1 shows the truth table of the SRAM block. Model the 6116 SRAM block using VHDL. You should incorporate the timing specifications of the 6116 block in your VHDL model by looking at its datasheet. A10 Memory Matrix Row Decoder 128 X 128 A4 ... 107 Column I/0 Input Data Column Decoder Control A3 A2 A1 Ao OE D WE CS Figure 1. Table 1. CS OE WE Mode /0 pins X Not selected High-Z High-Z Data out X Output disabled Read Write L…
- For load-store architecture, we have to load operands from memory anyways, as compared to register-memory architecture. Please answer why there are still benefits of reducing I/O traffic? Please show the benefit of load-store through an example of code.Logical address converted into linear address using then into physical address on memory using. A is a logically self-contained unit of code that receives a list of parameters and performs computation, and returns results The combines your program's object file created by the assembler with libraries to produces an executable program makes it possible to start an instruction before completing the execution of previous one. The architecture that has a small and simple instruction set with which all instructions have the same width Uses the system bus to communicate with the processor and to handle low-level operations The mode in which each program can address a maximum of 4 GB of memory. Expensive, used for cache memory, faster access, no refresh The table provided by the operating system contains segment descriptors for all programs and initialized during boot up. A special 32-bit register that indicates the address of the next instruction to be executed by the microprocessor…Problem 1. This problem is about operand modes, in particular about memory addressing using the operand modes described in lecture and the textbook. The following shows the contents of a portion of the program memory (locations Ox10000 through 0x10040), and certain registers. All contents are 64-bit quantities. Address Memory Contents 0x10040 0x10038 0x10030 0x10028 0x10020 0x10018 0x10010 0x10008 0x10000 a. movq (%rdi), %rax b. movq (%rdi,%rsi), %rax 100 0x10040 200 25 0x10028 0x10020 c. movq 8(%rdi, %rcx, 4) %r8 d. movq -8(%rdi,%rsi), rbx 500 0x10018 2 Register Contents %rdi 0x10008 %rsi %rdx %rcx For each of the following instructions, say what value ends up in the destination register. Each instruction starts with the state shown above, i.e., the effects do not accumulate. 0x20 8 4