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When processor designers consider a possible improvement to the processor datapath, the decision usually depends on the cost/performance trade-off . In the following problems, assume that we are starting with a datapath from Figure 4.2, where I-Mem, Add, Mux, ALU, Regs, D-Mem, and Control blocks have latencies of 4100ps, 110ps, 25ps, 120ps, 200ps, 320ps, and 120ps, respectively, and costs of 1050, 35, 15, 100, 200, 1750, and 550, respectively. Consider the addition of a multiplier to the ALU. This addition will add 250ps to the latency of the ALU and will add a cost of 500 to the ALU. The result will be 7.0% fewer instructions executed since we will no longer need to emulate the MUL instruction. What is the clock cycle time with and without this improvement?

When processor designers consider a possible improvement to the processor datapath, the decision usually depends on the cost/performance trade-off . In the following problems, assume that we are starting with a datapath from Figure 4.2, where I-Mem, Add, Mux, ALU, Regs, D-Mem, and Control blocks have latencies of 4100ps, 110ps, 25ps, 120ps, 200ps, 320ps, and 120ps, respectively, and costs of 1050, 35, 15, 100, 200, 1750, and 550, respectively. Consider the addition of a multiplier to the ALU. This addition will add 250ps to the latency of the ALU and will add a cost of 500 to the ALU. The result will be 7.0% fewer instructions executed since we will no longer need to emulate the MUL instruction. What is the clock cycle time with and without this improvement?

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Add PC Address Instruction Instruction memory Add Data Register # Register # Register # RegWrite Registers Control ALU operation Branch ALU Address Zero MemWrite Data Data memory MemRead When processor designers consider a possible improvement to the processor datapath, the decision usually depends on the cost/performance trade-off. In the following problems, assume that we are starting with a datapath from Figure 4.2, where I-Mem, Add, Mux, ALU, Regs, D-Mem, and Control blocks have latencies of 4100ps, 110ps, 25ps, 120ps, 200ps, 320ps, and 120ps, respectively, and costs of 1050, 35, 15, 100, 200, 1750, and 550, respectively. Consider the addition of a multiplier to the ALU. This addition will add 250ps to the latency of the ALU and will add a cost of 500 to the ALU. The result will be 7.0% fewer instructions executed since we will no longer need to emulate the MUL instruction. What is the clock cycle time with and without this improvement?
Transcribed Image Text:Add PC Address Instruction Instruction memory Add Data Register # Register # Register # RegWrite Registers Control ALU operation Branch ALU Address Zero MemWrite Data Data memory MemRead When processor designers consider a possible improvement to the processor datapath, the decision usually depends on the cost/performance trade-off. In the following problems, assume that we are starting with a datapath from Figure 4.2, where I-Mem, Add, Mux, ALU, Regs, D-Mem, and Control blocks have latencies of 4100ps, 110ps, 25ps, 120ps, 200ps, 320ps, and 120ps, respectively, and costs of 1050, 35, 15, 100, 200, 1750, and 550, respectively. Consider the addition of a multiplier to the ALU. This addition will add 250ps to the latency of the ALU and will add a cost of 500 to the ALU. The result will be 7.0% fewer instructions executed since we will no longer need to emulate the MUL instruction. What is the clock cycle time with and without this improvement?
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