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RegDst Branch MemRead MentoReg ALUOP MamWrite ALUSro RegWrte Shift left 2 Pi Add Instruction [31-28 Control PC Read address Instruction [31-0] Instruction memory Instruction [25-21] Instruction [20-16] Read Register 1 Read Register 2 Read Data 1 M U ADD X resul Add Zero Read ALU result Address Read data M M Data 2 ALU U Bata Memory x X M Instruction [15-11] Write Register Write Data Register File Instruction [15-0] Sign Extend The Simple Detonath with the Control Unit ALU Control Instruction [15-0] Write data

RegDst Branch MemRead MentoReg ALUOP MamWrite ALUSro RegWrte Shift left 2 Pi Add Instruction [31-28 Control PC Read address Instruction [31-0] Instruction memory Instruction [25-21] Instruction [20-16] Read Register 1 Read Register 2 Read Data 1 M U ADD X resul Add Zero Read ALU result Address Read data M M Data 2 ALU U Bata Memory x X M Instruction [15-11] Write Register Write Data Register File Instruction [15-0] Sign Extend The Simple Detonath with the Control Unit ALU Control Instruction [15-0] Write data

Systems Architecture
Systems Architecture
7th Edition
ISBN:9781305080195
Author:Stephen D. Burd
Publisher:Stephen D. Burd
Chapter4: Processor Technology And Architecture
Section: Chapter Questions
Problem 26VE: _____ is a CPU design technique in which instruction execution is divided into multiple stages and...
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Question 5a) For the single-cycle processor, what are the values (in binary) of instruction[31-26], instruction[25-21], instruction[20-16], instruction[15-11], instruction[5-0], Read data 1, Read data 2, ALU zero, PCSrc, and all the main control decoded output signals when the time is at 1950 ns. The figure of processor can be use.

Then fill in the following.

At the moment of 1950 ns, the below values (0, 1 or X) are:
instruction[31-26] = 
instruction[25-21] = 
instruction[20-16] = 
instruction[15-0] = 

Read data 1 output =

Read data 2 output =

MemWrite = 

Branch = 

ALUop[1:0] = 

ALU zero = 

PCSrc = 

RegDst = 

ALUSrc = 

MemtoReg = 

RegWrite = 

MemRead = 

RegDst Branch MemRead MentoReg ALUOP MamWrite ALUSro RegWrte Shift left 2 Pi Add Instruction [31-28 Control PC Read address Instruction [31-0] Instruction memory Instruction [25-21] Instruction [20-16] Read Register 1 Read Register 2 Read Data 1 M U ADD X resul Add Zero Read ALU result Address Read data M M Data 2 ALU U Bata Memory x X M Instruction [15-11] Write Register Write Data Register File Instruction [15-0] Sign Extend The Simple Detonath with the Control Unit ALU Control Instruction [15-0] Write data
Transcribed Image Text:RegDst Branch MemRead MentoReg ALUOP MamWrite ALUSro RegWrte Shift left 2 Pi Add Instruction [31-28 Control PC Read address Instruction [31-0] Instruction memory Instruction [25-21] Instruction [20-16] Read Register 1 Read Register 2 Read Data 1 M U ADD X resul Add Zero Read ALU result Address Read data M M Data 2 ALU U Bata Memory x X M Instruction [15-11] Write Register Write Data Register File Instruction [15-0] Sign Extend The Simple Detonath with the Control Unit ALU Control Instruction [15-0] Write data
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