Question 11) Assume there are four threads T1, T2, T3 and T4 with 100 instructions each. The instructions in each thread are dependent on the previous instruction, (for example in thread T1, 12 is dependent on I1, 13 on 12... so on) so that if I1 is issued in cycle x, 12 can be issued earliest at cycle x+2. The threads do not have any inter- thread dependency. Assume that each instruction takes one cycle to complete, and that the thread switching overhead is 2 cycles. a) Consider a single cycle MIPS processor with 1 PC and 1 Register File. If there is no interleaving of threads, meaning one thread completes before the start of the next thread, how many cycles are required for the completion of all four threads? b) For the same processor configuration, if there is a fine-grained multithreading of 1 instruction, what will be execution time in cycles for completion of all the four threads? Hint: I1 of T1 executes followed by a context switch to execute Il of T2... so on. If 11 of T1 is issued in cycle 1, the Il of T2 is issued in cycle 4 c) For the same processor configuration, if there is a coarse-grained multithreading of 10 instructions, how many cycles are required for the completion of all four threads? d) Now consider a single cycle MIPS processor with 4 PCs and 4 register files, and a single-issue hardware multithreading. How many cycles are required for the completion of all four threads? Hint: Each thread has its own PC and register file, so there is no context switching overhead, but each thread can issue only one instruction per cycle. For example, Il of r1 is issued at cycle 1, 11 of T2 is issued in cycle 2 and so on. e) Now consider a single cycle MIPS processor with 4 PCs and 4 Register Files, and a dual-issue simultaneous multithreading. How many cycles are required for the completion of all four threads? Hint: In This Case, Il1 of T1 and Il of T2 can be issued in cycle 1 followed by Il of T3 and I1 of T4 in cycle 2.