Question 1: Choose the correct answer: 1. In a 4-variable Karnaugh map, a 2-variable product term is produced by (a) a 2-cell group of 1s (b) an 8-cell group of 1s a 4-cell group of ls 2. (d) a 4-cell group of Os The expression ABCD + ABCD+ABCD 3. (a) cannot be simplified (b) can be simplified to ABC+AB (c) can be simplified to ABCD+ABC (d) None of these answers is correct The OR operation can be produced with (a) two NOR gates (c) four NAND gates (b) three NAND gates (d) both answers (a) and (b) 4. A 3-bit parallel adder can add (a) three 2-bit binary numbers ((c) three bits at a time 5. two 3-bit binary numbers (d) three bits in sequence If a 1-of-16 decoder with active -LOW outputs exhibits a LOW on the decimal 12 output, what are the outputs? (a) A3A2A1A0=1010 (c) A3A2A1A0=1100 Question 2: (b) A3A2A1A0=1110 (d) A3A2A1A0-0100 1. Draw the logical symbol of the full-adder. 2. Generate its truth table. 3. Determine the minimum logical expression for the Sum and the Carry out using K-map. Question 3: A. Use minimum number of NAND gates to implement the following logic circuit, A D CDF B B. Use multiplexer only to implement the following logic gates: 1. XOR. 2. NOT. (8 Not=
Question 1: Choose the correct answer: 1. In a 4-variable Karnaugh map, a 2-variable product term is produced by (a) a 2-cell group of 1s (b) an 8-cell group of 1s a 4-cell group of ls 2. (d) a 4-cell group of Os The expression ABCD + ABCD+ABCD 3. (a) cannot be simplified (b) can be simplified to ABC+AB (c) can be simplified to ABCD+ABC (d) None of these answers is correct The OR operation can be produced with (a) two NOR gates (c) four NAND gates (b) three NAND gates (d) both answers (a) and (b) 4. A 3-bit parallel adder can add (a) three 2-bit binary numbers ((c) three bits at a time 5. two 3-bit binary numbers (d) three bits in sequence If a 1-of-16 decoder with active -LOW outputs exhibits a LOW on the decimal 12 output, what are the outputs? (a) A3A2A1A0=1010 (c) A3A2A1A0=1100 Question 2: (b) A3A2A1A0=1110 (d) A3A2A1A0-0100 1. Draw the logical symbol of the full-adder. 2. Generate its truth table. 3. Determine the minimum logical expression for the Sum and the Carry out using K-map. Question 3: A. Use minimum number of NAND gates to implement the following logic circuit, A D CDF B B. Use multiplexer only to implement the following logic gates: 1. XOR. 2. NOT. (8 Not=
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Digital electronics
Transcribed Image Text:Question 1:
Choose the correct answer:
1.
In a 4-variable Karnaugh map, a 2-variable product term is produced by
(a) a 2-cell group of 1s
(b) an 8-cell group of 1s
a 4-cell group of ls
2.
(d) a 4-cell group of Os
The expression ABCD + ABCD+ABCD
3.
(a) cannot be simplified
(b) can be simplified to ABC+AB
(c) can be simplified to ABCD+ABC (d) None of these answers is correct
The OR operation can be produced with
(a) two NOR gates
(c) four NAND gates
(b) three NAND gates
(d) both answers (a) and (b)
4.
A 3-bit parallel adder can add
(a) three 2-bit binary numbers
((c) three bits at a time
5.
two 3-bit binary numbers
(d) three bits in sequence
If a 1-of-16 decoder with active -LOW outputs exhibits a LOW on the decimal 12 output, what
are the outputs?
(a) A3A2A1A0=1010
(c) A3A2A1A0=1100
Question 2:
(b) A3A2A1A0=1110
(d) A3A2A1A0-0100
1. Draw the logical symbol of the full-adder.
2. Generate its truth table.
3. Determine the minimum logical expression for the Sum and the Carry out
using K-map.
Question 3:
A. Use minimum number of NAND gates to implement the following logic circuit,
A
D
CDF
B
B. Use multiplexer only to implement the following logic gates:
1. XOR.
2. NOT.
(8
Not=
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