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QUESTION 1 A program runs on a processor of two levels of cache. We know the following: L1 cache access time: 1 clock cycle L1 cache miss rate: 10% L2 cache access time: 10 clock cycles L2 cache miss rate (local miss rate): 20% main memory access time: 200 cycles. What is the AMAT (average memory access time)? QUESTION 2

QUESTION 1 A program runs on a processor of two levels of cache. We know the following: L1 cache access time: 1 clock cycle L1 cache miss rate: 10% L2 cache access time: 10 clock cycles L2 cache miss rate (local miss rate): 20% main memory access time: 200 cycles. What is the AMAT (average memory access time)? QUESTION 2

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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QUESTION 1 A program runs on a processor of two levels of cache. We know the following: L1 cache access time: 1 clock cycle L1 cache miss rate: 10% L2 cache access time: 10 clock cycles L2 cache miss rate (local miss rate): 20% main memory access time: 200 cycles. What is the AMAT (average memory access time)? QUESTION 2 This question continues Question 1. We have additional information about this program: load instruction percentage: 35% store instruction percentage: 15% How many memory accesses per instruction will happen? Note: This question is not asking about main memory accesses.
Transcribed Image Text:QUESTION 1 A program runs on a processor of two levels of cache. We know the following: L1 cache access time: 1 clock cycle L1 cache miss rate: 10% L2 cache access time: 10 clock cycles L2 cache miss rate (local miss rate): 20% main memory access time: 200 cycles. What is the AMAT (average memory access time)? QUESTION 2 This question continues Question 1. We have additional information about this program: load instruction percentage: 35% store instruction percentage: 15% How many memory accesses per instruction will happen? Note: This question is not asking about main memory accesses.
QUESTION 3 This question continues from Questions 1&2. What is the number of L1 misses per instruction? QUESTION 4 This question continues from Questiab 1-3. What is the number of L2 misses per instruction?
Transcribed Image Text:QUESTION 3 This question continues from Questions 1&2. What is the number of L1 misses per instruction? QUESTION 4 This question continues from Questiab 1-3. What is the number of L2 misses per instruction?
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