Q7. A processor has a clock frequency of 1GHZ, we run a program consisting 10 billion instructions on this processor. The program has the following instruction mix. (07.1 & Q7.2 use same information Instruction class ALU Branch Jump Load Store % of program 50% 30% 10% 5% 5% Q7.2 The execution times in seconds is a) 3.65 b) 3.55 c) 35.5 d) Non of the above CPI 4 3 2 5

Q7. A processor has a clock frequency of 1GHZ, we run a program consisting 10 billion instructions on this processor. The program has the following instruction mix. (07.1 & Q7.2 use same information Instruction class ALU Branch Jump Load Store % of program 50% 30% 10% 5% 5% Q7.2 The execution times in seconds is a) 3.65 b) 3.55 c) 35.5 d) Non of the above CPI 4 3 2 5

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Write the MIPS code of the below given C code. Also identify type of each instruction and encode all the instructions. Assume that X, Y are in register $3, and $4 respectively and base address of A is in register $4. A [3] =7*X+9*Y+100; X=12*A [A [2]] +21*Y-30; Y=A[X]+A[X+2];
Computer Science
Q2: Answer the following: A: What is the machine language equivalent for this instruction that appear in a program? SBB AX. [BP+65H]; Where the Op code for (SBB-000110) 2. MOV SS:[BP+DI+23A1], CX; where the opcode for (MOV = 100010) Table 1. MOD field for the 16-bit instruction mode Table 2. 16-bit R/M memory - addressing mo MOD Function R/M Code Addressing Mode 00 No displacement 000 DS:[BX+SI] 01 001 DS:[BX+DI] 8-bit sign-extended displacement 16-bit signed displacement 10 010 SS:[BP+SI] 11 R/M is a register 011 SS:[BP+DI] 100 DS:[SI] 101 DS:[DI] 110 SS:[BP]* 111 DS:[BX] Table 3. REG and R/M when MOD = 11 assignments Code W = 0 (Bytc) W = 1 (Word) 000 AL AX 001 CL CX 010 DL DX 011 BL BX 100 AH SP 101 CH BP 110 DH SI 111 BH DI W = 1 (Doubleword) EAX ECX EDX EBX ESP EBP ESI EDI
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// Example 8.27a void Func(int a[], int & r) { int i; for (i = 0; i < 100; i++) { a[i] = r + i/2; }} The Intel assembler produces the following assembly code from Example 8.27a (32 bit mode): don't copy old bartleby answer it's wrong.
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QUESTION 3 Evaluate the statement below and show how to compile it into MIPS (Million Instructions Per Second) code by using instruction set machine of three-address, two-address and one-address. F = X/Y + V - W
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[2] ( Explain for each line why you chose a certain suffix such as b,w,l or q For each of the following lines of assembly language, determine the appropriate instruction suffix based on the operands. (For example, mov can be rewritten as movb, movw, movl, or movq.) mov mov mov που mov που Zeax, (%rap) (%rax), %dx $0xFF, %bl (%rap,%rdx, 4), %d1 (%rdx), %rax %dx, (%rax)
1. Consider a machine running a program with four classes of instructions: A/B/C/D. The program requires 360 seconds, with the number of seconds executing each class as shown in the table below: Instruction Class A B C Time (sec) 100 80 120 60 1.1. By how much is the total execution time changed if the time for class D is reduced by 20% and the time for class C is increased by 10% (assuming no other changes)? 1.2. If we want to reduce the total execution time by 20% by optimizing class A only, what is the target execution time of class A instructions in order to achieve the reduction (assuming all other instructions are not changed)? 1.3. Can the total time be reduced by 25% if we only optimize class B? Use calculation to justify your answer.
E In the following code block(Reference:Q11), you will a set of assembly instructions with corresponding line numbers (line numbers are for informational purpose only and they are not part of the source code). 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 mov edx, 5 dec ecx jmp LABEL1 mov eax, 1 LABEL1: mul edx jmp ecx mov edx, 0678h sub edx, eax jmp DWORD PTR [edx] neg ebx add ecx, ebx mov eax, 0 For each of the conditions/scenario listed below, indicate the corresponding line number (that cause or is associated with the condition/scenario). Enter 0 (Zero) if the condition is not caused by the block of code. 1) Memory indirect jump: type your answer... type your answer... type your answer... type your answer... 2) Register indirect jump: 3) Relative short jump: type your answer... 5) Two's complement type your answer... 4) Relative near jump: 6) Unreachable code