Q1. (a) Design a stick diagram for the following static CMOS logic gate, where A, B, C, D are the logic gate inputs and O/P is the output: 3-d[Q6 B c-d[Q7 D-d [Q8 A - Q5 D AQ1 C !!! B Q4 Q3 Q2 VDD O/P Assume VDD = 5 V, K'n = 50 µA/V², K'p = 20 μA/V² Vss Figure 1 Use dual-well, CMOS technology. Include wells, well-taps, contact cuts, routing of power and GND in your diagram. Use colour coding and/or clear and readable detailed annotations to represent the wires in the different layers. (b) The logic gate from (a) needs to drive a capacitive load of 150 ff with a rise- time and fall-time of 0.5 ns. If the length of all transistors is 0.5 µm, calculate the required widths for all P-type and all N-type MOSFETs in your logic gate to achieve the required edge-speeds. Clearly show the calculation steps in your solution.
Q1. (a) Design a stick diagram for the following static CMOS logic gate, where A, B, C, D are the logic gate inputs and O/P is the output: 3-d[Q6 B c-d[Q7 D-d [Q8 A - Q5 D AQ1 C !!! B Q4 Q3 Q2 VDD O/P Assume VDD = 5 V, K'n = 50 µA/V², K'p = 20 μA/V² Vss Figure 1 Use dual-well, CMOS technology. Include wells, well-taps, contact cuts, routing of power and GND in your diagram. Use colour coding and/or clear and readable detailed annotations to represent the wires in the different layers. (b) The logic gate from (a) needs to drive a capacitive load of 150 ff with a rise- time and fall-time of 0.5 ns. If the length of all transistors is 0.5 µm, calculate the required widths for all P-type and all N-type MOSFETs in your logic gate to achieve the required edge-speeds. Clearly show the calculation steps in your solution.
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
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Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Transcribed Image Text:Q1. (a) Design a stick diagram for the following static CMOS logic gate, where A, B,
C, D are the logic gate inputs and O/P is the output:
B-d[Q6
c-d[Q7
A - Q5
AQ1
D
B
D-d [Q8
C H[Q3
40 Q2
Figure 1
Q4
VDD
O/P
Assume VDD = 5 V, K'n = 50 μA/V², K'p = 20 μA/V²
Vss
Use dual-well, CMOS technology. Include wells, well-taps, contact cuts, routing
of power and GND in your diagram. Use colour coding and/or clear and readable
detailed annotations to represent the wires in the different layers.
(b) The logic gate from (a) needs to drive a capacitive load of 150 ff with a rise-
time and fall-time of 0.5 ns. If the length of all transistors is 0.5 µm, calculate the
required widths for all P-type and all N-type MOSFETs in your logic gate to
achieve the required edge-speeds. Clearly show the calculation steps in your
solution.
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