circuits, pleaseeeee solve questionnn B:4 Fig. 1 shows an oscillator circuit using 555 timer, with RA = 1.5KQ, RB =2.5KQ Vcc= 12 V, and C= 0.7215uF. Assume the diode is ideal, then123If the diode is disconnected, then456The charging time (T,) (in ms)The duty cycle (ratio)The frequency of the output signal (in Hz)1016The discharging time (T₂) (in ms)The duty cycle (ratio)The frequency of the output signal (in Hz)V R₁RARB11+VccDischargeThresholdTriggerGroundD,Fig 3Reset555 Output+125-12+Vcc45voVEEA1.250.375666.7The minimum output voltageDraw to scale the transfer characteristics.Draw to scale the input and the output signals when Vin is a triangle wave of 8 Vp-p1.50.615500Voltage transfer c/cwwREVERFig. 1Fig. 2Consider the sweep generator circuit shown in Fig. 2 where RE = 4KS2, RB = 4.7K2, VEE=30.7V, VBB= 20V, and C= 0.5 uF.The control signal (v) has a pulse duration of 0.5ms, a frequency of 500Hz, and a +12V amplitude. Then72.53.589The emitter current I (in mA)The charging time of the capacitor (in ms)2.5The peak voltage of the capacitor (Vp)6.0The minimum value of Rg that we can use and still obtain a linear sweep 1.5waveform (in K2)Consider a Schmitt trigger circuit with ± VSAT = 12 V, Vur=4V, and Vir=0 V. This circuit is modified to be an oscillatorcircuit by adding C= 3.46 µF and R=2 KS2. Then11 The charging time (Tch) of this circuit (in msec) is2.812 The discharging time (Tdisch) of this circuit ( in msec ) is3.0Consider the circuit shown in Fig. 3 where Vzi = 3.3V, VA= 4.3V, and ± VSAT = ±12 V. Then13 The maximum output voltage4.05.014-4.0- 5.015BC0.51.00.667 0.333307.85001.44.01.750.6307.71.250.54002.03.010.51.82821.59.01.24.21.0D0.750.54001.00.75666.7R₂12-0.7LI3.02.07.52.11995.62.0Yourans.0.7- 12input and output Prob. B.2: Consider the circuit shown in Fig. 4 where R-2K and C-0.667 pF. Thena. The frequency of the oscillation at the output isC-b. The frequency and the duty cycle of Vf0 to get an output of 4 pulses ON and 3 pulses OFF are:(-.D.R. -c. Draw the waveform of ve and v, for the above case.wwwwwHHFig. 4Prob. B3: Neglecting the base currents in the circuit shown in Fig. 5.a. Determine Rez such that v₂-1 V when Q₂ is ON and Q₁ is OFF.b. For v=-0.7, determine Re, such that v, --1 V.c. Find Vos and Voz for(1)--0.7 V.a. Rez-c. (1) VOI-34.777421AL GI-010Van'wwwwww(ii) Voi41041Fig. 5Preb. B.4: Consider the CMOS logic circuit shown in Fig. 6.a. What is the logic function performed by the circuit?Y-Veo-33VNMOSNetworkb. Rc-Fig. 6input and output(ii) V-1.7 V.Prob. B.S: Consider the R/2R ladder 4-bits D/A converter circuit shown below where Vsr-115V, V-4V, R,-20KC2, and R-10KT2. FindVo₂=a the output voltage for digital inputs 0010, 0101, and 1011.b. the minimum value of R and still get correct integer output representation for the digital input.The designed NMOS networkb. Design the NMOS network.b. R-Digital input001001011011Output voltage

Answered: Image /qna-images/answer/ab1ab792-1e19-412e-b6bc-6110ccab8311.jpg

Prob. B.2: Consider the circuit shown in Fig. 4 where R-2K and C-0.667 pF. Then a. The frequency of the oscillation at the output is C- b. The frequency and the duty cycle of 0 to get an output of 4 pulses ON and 3 pulses OFF are: D.R.-> c. Draw the waveform of ve and v, for the above case. wwwwww Fig. 4 Preb. B3: Neglecting the base currents in the circuit shown in Fig. 5. a. Determine Rez such that ₂--1 V when Q₂ is ON and Q, is OFF. b. For v--0.7, determine Rer such that v, --1 V. c. Find For and Voz for ()--0.7 V. a. Rc- c. (1) VOI- -42V Fig. 5 Voz" Freb. B4: Consider the CMOS logic circuit shown in Fig. 6. a. What is the logic function performed by the circuit? Y- 44 (ii) Vo GI NMOS Fig. 6 b. Rct input and output (ii) -1.7 V. Vo₂= The designed NMOS network Preb. BS Consider the R2R ladder 4-bits D/A converter circuit shown below where Vsr-115V, V-4V, R₂- 20KC2, and R-10KT2. Find b. Design the NMOS network. a the output voltage for digital inputs 0010, 0101, and 1011. b. the minimum value of R and get correct integer output representation for the digital input Digital input 0010 0101 1011 Output voltage

Prob. B.2: Consider the circuit shown in Fig. 4 where R-2K and C-0.667 pF. Then a. The frequency of the oscillation at the output is C- b. The frequency and the duty cycle of 0 to get an output of 4 pulses ON and 3 pulses OFF are: D.R.-> c. Draw the waveform of ve and v, for the above case. wwwwww Fig. 4 Preb. B3: Neglecting the base currents in the circuit shown in Fig. 5. a. Determine Rez such that ₂--1 V when Q₂ is ON and Q, is OFF. b. For v--0.7, determine Rer such that v, --1 V. c. Find For and Voz for ()--0.7 V. a. Rc- c. (1) VOI- -42V Fig. 5 Voz" Freb. B4: Consider the CMOS logic circuit shown in Fig. 6. a. What is the logic function performed by the circuit? Y- 44 (ii) Vo GI NMOS Fig. 6 b. Rct input and output (ii) -1.7 V. Vo₂= The designed NMOS network Preb. BS Consider the R2R ladder 4-bits D/A converter circuit shown below where Vsr-115V, V-4V, R₂- 20KC2, and R-10KT2. Find b. Design the NMOS network. a the output voltage for digital inputs 0010, 0101, and 1011. b. the minimum value of R and get correct integer output representation for the digital input Digital input 0010 0101 1011 Output voltage

Introductory Circuit Analysis (13th Edition)

13th Edition

ISBN:9780133923605

Author:Robert L. Boylestad

Publisher:Robert L. Boylestad

Chapter1: Introduction

Section: Chapter Questions

Problem 1P: Visit your local library (at school or home) and describe the extent to which it provides literature...

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