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Part 2 - Design of Boolean Logics Gray code (GC) is a binary code that ensures that from one transition to another, there is only a single one-bit value that changes, as illustrated with the following Truth table. We aim to design a Ray code conversion system. Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 (F3 F₂ F₁ Fo) Gray code 0000 0001 0011 0010 0110 0111 0101 0100 1100 1101 1111 1110 1010 1011 1001 1000 For each GC output named F in (F3F₂ F₁ Fo) a. Write a simplified Boolean expression of each F output using K-maps b. Derive the product of sum canonical form of F then write F using maxterms using the same K-map c. Draw the gates diagram of F₂ using AND, OR and NOT gates (use only 2 inputs gates) d. Draw the gate diagram of F₁ using NANDS and be sure to apply all possible gate simplifications. Count the number of NANDS used to implement F₁ e. Implement F₁ using a 16 to 1 simple multiplexer f. Implement F₁ using 8 to 1 multiplexers g. Implement F₁ using a 4 to 16 simple decoder h. Implement F, using 3 to 8 with enable decoder

Part 2 - Design of Boolean Logics Gray code (GC) is a binary code that ensures that from one transition to another, there is only a single one-bit value that changes, as illustrated with the following Truth table. We aim to design a Ray code conversion system. Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 (F3 F₂ F₁ Fo) Gray code 0000 0001 0011 0010 0110 0111 0101 0100 1100 1101 1111 1110 1010 1011 1001 1000 For each GC output named F in (F3F₂ F₁ Fo) a. Write a simplified Boolean expression of each F output using K-maps b. Derive the product of sum canonical form of F then write F using maxterms using the same K-map c. Draw the gates diagram of F₂ using AND, OR and NOT gates (use only 2 inputs gates) d. Draw the gate diagram of F₁ using NANDS and be sure to apply all possible gate simplifications. Count the number of NANDS used to implement F₁ e. Implement F₁ using a 16 to 1 simple multiplexer f. Implement F₁ using 8 to 1 multiplexers g. Implement F₁ using a 4 to 16 simple decoder h. Implement F, using 3 to 8 with enable decoder

Introductory Circuit Analysis (13th Edition)
Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
Section: Chapter Questions
Problem 1P: Visit your local library (at school or home) and describe the extent to which it provides literature...
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Part 2 - Design of Boolean Logics Gray code (GC) is a binary code that ensures that from one transition to another, there is only a single one-bit value that changes, as illustrated with the following Truth table. We aim to design a Ray code conversion system. Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 (F3 F₂ F₁ F₁) Gray code 0000 0001 0011 0010 0110 0111 0101 0100 1100 1101 1111 1110 1010 1011 1001 1000 For each GC output named Fin (F3 F₂ F₁ Fo) a. Write a simplified Boolean expression of each F output using K-maps b. Derive the product of sum canonical form of F then write F using maxterms using the same K-map C. Draw the gates diagram of F₁ using AND, OR and NOT gates (use only 2 inputs gates) d. Draw the gate diagram of F₁ using NANDS and be sure to apply all possible gate simplifications. Count the number of NANDS used to implement F₁ e. Implement F₁ using a 16 to 1 simple multiplexer f. Implement F₁ using 8 to 1 multiplexers g. Implement F₁ using a 4 to 16 simple decoder h. Implement F₁ using 3 to 8 with enable decoder
Transcribed Image Text:Part 2 - Design of Boolean Logics Gray code (GC) is a binary code that ensures that from one transition to another, there is only a single one-bit value that changes, as illustrated with the following Truth table. We aim to design a Ray code conversion system. Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 (F3 F₂ F₁ F₁) Gray code 0000 0001 0011 0010 0110 0111 0101 0100 1100 1101 1111 1110 1010 1011 1001 1000 For each GC output named Fin (F3 F₂ F₁ Fo) a. Write a simplified Boolean expression of each F output using K-maps b. Derive the product of sum canonical form of F then write F using maxterms using the same K-map C. Draw the gates diagram of F₁ using AND, OR and NOT gates (use only 2 inputs gates) d. Draw the gate diagram of F₁ using NANDS and be sure to apply all possible gate simplifications. Count the number of NANDS used to implement F₁ e. Implement F₁ using a 16 to 1 simple multiplexer f. Implement F₁ using 8 to 1 multiplexers g. Implement F₁ using a 4 to 16 simple decoder h. Implement F₁ using 3 to 8 with enable decoder
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