output voltage for each step listed. 4. Redesign the circuit so that the input voltage of V, has an increase gain of 5 and V2 is reduced in gain by a factor of 10. The input voltage of Va is to have unity gain. Describe this procedure in your lab report in detail, and build this circuit. thnt the innut voltagAR gre: V.=1 2 V-=0,5. and
output voltage for each step listed. 4. Redesign the circuit so that the input voltage of V, has an increase gain of 5 and V2 is reduced in gain by a factor of 10. The input voltage of Va is to have unity gain. Describe this procedure in your lab report in detail, and build this circuit. thnt the innut voltagAR gre: V.=1 2 V-=0,5. and
Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
Section: Chapter Questions
Problem 1P: Visit your local library (at school or home) and describe the extent to which it provides literature...
Related questions
Question
# 4. Give me a description of the procedure in detail.
![2.
3.
ーる0n
[N+AZキハンロー
R1
10KS2
5k2/75%
+15V
R2
AG L+
十ASで+ N.
Stn2コ-
SHO L
R3
AL-
15V
「A1+AS+Aてコー2
19-2
3. Reset the input potentiometer to meet the specified input voltages for each step listed in Table 1.
Calculate expected output voltages and record in the table. Also measure and record in Table 1 the
2U+ output voltage for each step listed.
4. Redesign the circuit so that the input voltage of V, has an increase gain of 5 and V2 is reduced in
7N gain by a factor of 10. The input voltage of V3 is to have unity gain. Describe this procedure in your
lab report in detail, and build this circuit.
5. Set the potentiometers so that the input voltages are: V,-1.2, V2-0.5, and
V3= -2.5V to your redesigned circuit. Measure Vout. Calculate the theoretical value of V Dut- Discuss
any differences between the measured and calculated values.
Table 1. Summing Amplifier Calculated and Measured Output
V2
V3
Vout (calc.)
Vout (meas.)
1.5
2.0
1.5
2.5
3.0
L-
-14.98
4.0
b99
5.0
6.0
2.0
3.0
-6
3.48
4.
80.9
-2.0
-4.5
5.5
-2.0
-7.0
Cala
9.
40
1.240
ひる2021)
3.5
Meajured](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F585e4a80-646c-4418-ada9-cb992a2ce44b%2F31d42753-c8cf-48a3-9ac5-816585cba910%2Fmcwolv.jpeg&w=3840&q=75)
Transcribed Image Text:2.
3.
ーる0n
[N+AZキハンロー
R1
10KS2
5k2/75%
+15V
R2
AG L+
十ASで+ N.
Stn2コ-
SHO L
R3
AL-
15V
「A1+AS+Aてコー2
19-2
3. Reset the input potentiometer to meet the specified input voltages for each step listed in Table 1.
Calculate expected output voltages and record in the table. Also measure and record in Table 1 the
2U+ output voltage for each step listed.
4. Redesign the circuit so that the input voltage of V, has an increase gain of 5 and V2 is reduced in
7N gain by a factor of 10. The input voltage of V3 is to have unity gain. Describe this procedure in your
lab report in detail, and build this circuit.
5. Set the potentiometers so that the input voltages are: V,-1.2, V2-0.5, and
V3= -2.5V to your redesigned circuit. Measure Vout. Calculate the theoretical value of V Dut- Discuss
any differences between the measured and calculated values.
Table 1. Summing Amplifier Calculated and Measured Output
V2
V3
Vout (calc.)
Vout (meas.)
1.5
2.0
1.5
2.5
3.0
L-
-14.98
4.0
b99
5.0
6.0
2.0
3.0
-6
3.48
4.
80.9
-2.0
-4.5
5.5
-2.0
-7.0
Cala
9.
40
1.240
ひる2021)
3.5
Meajured
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