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Engineering

Computer Science

Objective: Show the influence of the cache size on the miss rate

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter6: System Integration And Performance

Section: Chapter Questions

Problem 22VE

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Concept explainers

Fundamentals of memory

A collection of connected storage devices form the memory unit. It is a space to store data and instructions required for processing. Information is stored in a memory unit in the form of bits. There are two types of memory namely:

Question

Please explain problem 1, a, and b

1. Objective: Show the influence of the cache size on the miss rate

Development Configure a system with the following architectural characteristics:

•Processors in SMP = 1

•Cache coherence protocol = MESI

•Scheme for bus arbitration = Random

•Word wide (bits) = 16

•Words by block = 16 (block size = 32 bytes)

•Blocks in main memory = 8192 (main memory size = 256 KB)

•Mapping = Fully-associative•Replacement policy = LRU

Configure the blocks in cache using the following configurations: 2(cache size = 0,03 KB), 4,8, 16, 32, 64, 128, 256, and 512 (cache size = 16 KB).

For each of the configurations, obtain the miss rate using the trace files : Hydro, Naasa7, Cexp, Comp, and Wave.

a. Does the miss rate increase or decrease as the cache sizes increases? Why?

b. Does the increase of cache size improve the system performance?

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