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O maps to physical frame 2, page 1 maps to frame 0, page 2 maps to frame 1, and page 3 is not mapped to any physical frame. The process may not use more than 3 physical frames. On a page fault, the demand paging system uses the LRU policy to evict a page. The MMU has a TLB cache that can store 2 entries. The TLB cache also uses the LRU policy to store the most recently used mappings in cache. Now, the process accesses the following logical addresses in order: 23, 16, 47, 42, 3, 63, 33 Out of the 7 memory accesses, clearly indicate whether the accesses result in a hit or miss. Assume that the TLB cache is empty before the accesses begin 23 - 16 - 47 - 42 - 3 - 63 - 33 - Out of the 7 memory accesses, which resulted in a page fault? Please answer with the page number associated with that memory access (e.g. 7) Which page under LRU would be replaced with the page which caused the page fault?

O maps to physical frame 2, page 1 maps to frame 0, page 2 maps to frame 1, and page 3 is not mapped to any physical frame. The process may not use more than 3 physical frames. On a page fault, the demand paging system uses the LRU policy to evict a page. The MMU has a TLB cache that can store 2 entries. The TLB cache also uses the LRU policy to store the most recently used mappings in cache. Now, the process accesses the following logical addresses in order: 23, 16, 47, 42, 3, 63, 33 Out of the 7 memory accesses, clearly indicate whether the accesses result in a hit or miss. Assume that the TLB cache is empty before the accesses begin 23 - 16 - 47 - 42 - 3 - 63 - 33 - Out of the 7 memory accesses, which resulted in a page fault? Please answer with the page number associated with that memory access (e.g. 7) Which page under LRU would be replaced with the page which caused the page fault?

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Consider a system with 8-bit physical addresses and 16-byte pages. A process in this system has 4 logical pages, which are mapped to 3 physical frames in the following manner: logical page O maps to physical frame 2, page 1 maps to frame 0, page 2 maps to frame 1, and page 3 is not mapped to any physical frame. The process may not use more than 3 physical frames. On a page fault, the demand paging system uses the LRU policy to evict a page. The MMU has a TLB cache that can store 2 entries. The TLB cache also uses the LRU policy to store the most recently used mappings in cache. Now, the process accesses the following logical addresses in order: 23, 16, 47, 42, 3, 63, 33 Out of the 7 memory accesses, clearly indicate whether the accesses result in a hit or miss. Assume that the TLB cache is empty before the accesses begin 23 16 - 47 42 - 3 - 63 33 Out of the 7 memory accesses, which resulted in a page fault? Please answer with the page number associated with that memory access (e.g. 7) Which page under LRU would be replaced with the page which caused the page fault? Upon accessing the logical address 60, which physical address is eventually accessed by the system (after servicing any page faults that may arise)? Please leave your answer in binary with no spaces
Transcribed Image Text:Consider a system with 8-bit physical addresses and 16-byte pages. A process in this system has 4 logical pages, which are mapped to 3 physical frames in the following manner: logical page O maps to physical frame 2, page 1 maps to frame 0, page 2 maps to frame 1, and page 3 is not mapped to any physical frame. The process may not use more than 3 physical frames. On a page fault, the demand paging system uses the LRU policy to evict a page. The MMU has a TLB cache that can store 2 entries. The TLB cache also uses the LRU policy to store the most recently used mappings in cache. Now, the process accesses the following logical addresses in order: 23, 16, 47, 42, 3, 63, 33 Out of the 7 memory accesses, clearly indicate whether the accesses result in a hit or miss. Assume that the TLB cache is empty before the accesses begin 23 16 - 47 42 - 3 - 63 33 Out of the 7 memory accesses, which resulted in a page fault? Please answer with the page number associated with that memory access (e.g. 7) Which page under LRU would be replaced with the page which caused the page fault? Upon accessing the logical address 60, which physical address is eventually accessed by the system (after servicing any page faults that may arise)? Please leave your answer in binary with no spaces
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