Suppose there is a paging system with a translation lookaside buffer. Assuming that the entire page table and all the pages are in the physical memory, what is the effective memory access time in ms if it takes 5 msec to search the TLB and 70 msec to access physical memory? The TLB hit ratio is 0.8.
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- A computer uses virtual memory, and a new solid-state drive (SSD) as space for paging. Refer to the last ppt file. In the case presented there, the hard disk drive (HDD) required 25 ms to read in a page, and a rate of 1 page fault per 1000 references introduced a 250 slowdown. If the SSD offers a time of only 80 µs, what is the slowdown in performance caused by 1 pf per 1000 references (you are not concerned with dirty vs. clean pages). What is the maximum rate of page faults you can accept if you want no more than a 5% slowdown in execution using virtual memory? Know your metric prefixes and symbols for time: s for seconds, ms for milliseconds, µs for microseconds, ns for nanoseconds.Consider a paging system with the page table stored in memory.a. If a memory reference takes 400 nanoseconds, how long does a paged memoryreference take?b. If we add TLBs, and 95 percent of all page-table references are found in the TLBs,what is the effective memory reference time? (Assume that finding a page-table entry inthe TLBs takes zero time, if the entry is there.)A disk has a capacity of two tera-byte size. Say the file system uses a multi-level inode structure for locating the data blocks of afile.The inode stores pointers to data blocks, including a single indirect block, a double indirect block, and several direct blocks in the 64 B of available space.Now, it is given that the disk has a block size of 512 B. The maximum file size that can be stored in such a file system in MB (round off upto 2 decimal places).
- Consider a demand-paging system with a paging disk that has an average access and transfer time of 25 milliseconds. Addresses are translated through a page table in main memory, with an access time of 1 microsecond per memory access. Thus, each memory reference through the page table takes two accesses. To improve this time, we have added an associative memory that reduces access time to one memory reference if the page-table entry is in the associative memory. Assume that 75 percent of the accesses are in the associative memory and that, of those remaining, 10 percent (or 2.5 percent of the total) cause page faults. What is the effective memory access time?please no chatgpt answer . Consider a demand-paging system with a paging disk that has an average access and transfer time of 20 milliseconds. Addresses are translated through a page table in main memory, with an access time of 1 microsecond per memory access. Thus, each memory reference through the page table takes two accesses. To improve this time, we have added an associative memory that reduces access time to one memory reference, if the page-table entry is in the associative memory. Assume that 80 percent of the accesses are in the associative memory and that, of those remaining, 10 percent (or 2 percent of the total) cause page faults. What is the effective memory access time? Consider the following page reference string: 1, 2, 3, 4, 2, 1, 5, 6, 2, 1, 2, 3, 7, 6, 3, 2, 1, 2, 3, 6. Assuming demand paging with four frames, Show which pages are resident under the LRU, FIFO, and Optimal replacement algorithms by filling out the following tables. How many page faults would occur…It is given that on a system, on average, an instruction executes in 1 nano second. Suppose that it takes 20 micro seconds of processor time for page fault. While, it takes 300 micro seconds of disk time for reading and writing a single page. Suppose that on average 1/3 of the pages that need to be paged out are modified. What is the average number of instructions between page faults that would cause the disk to be busy doing page transfers all the time?
- In the working set model, the idea is to examine the most recent A page references. It is also known as an approximation of the Program's Locality. If the total demand is greater than the total number of available frames (D > m), then it will cause thrashing, because in this case, some processes will not have enough frames. Below you see 3 processes and their expected memory references during their execution. When will the thrashing happen to occur according to the Working set model? Assume total memory (m) is 13 and Delta (A ) is 5. Time: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 2 6 2 2 6 2 6 2 1 2 4 3 5 4 5 4 6 P1= I 8 6 I 8 6 I 9 4 9 8 I 6 9 9 9 9 P2= P3= 6 2 3 2 6 6 6 6 6 2 1 4 2 2 2 2 2Consider a fully-associative cache of size 4. Each slot in the cache can have just one item (i.e. the line size is 1 item). The cache is empty to start with. The cache uses an LRU replacement policy: every slot has a counter; every time a slot is accessed, a global counter is incremented and the value is stored in the slot counter; the slot with the lowest counter value is chosen for replacement. Sequence Id 1 2 3 4 5 6 7 8 10 Address Ox0012 0x0014 Ox0016 Ox0018 0x0016 0x0012 0x0020 Ox0022 0x0014 Ox0012 Hit/Miss Accesses 1 to 10 are respectively: Select one: O a. Miss, Miss, Miss, Miss, Hit, Hit, Miss, Miss, Miss, Miss O b. Miss, Miss, Miss, Miss, Hit, Hit, Miss, Miss, Hit, Hit O. Miss, Miss, Miss, Miss, Hit, Hit, Miss, Miss, Hit, Miss O d. Miss, Miss, Miss, Miss, Hit, Miss, Miss, Miss, Miss, Hit O e. Miss, Miss, Miss, Miss, Hit, Hit, Miss, Miss, Miss, HitConsider an ordered disk queue with requests involving tracks 97,145,22,14,124,65 and 67. if the read write head is initially at track 53, what is the total distance that the disk are moves to satisfy all the pending request for C-SCAN? E E E E E ΣΕ GHO
- A paging scheme uses a Translation Look-aside Buffer (TLB). A TLB-access takes 10 ns and a main memory access takes 50 ns. The effective access time(in ns) is_?(if the TLB hit ratio is 90% and there is no page-fault)In a main memory-disk virtual storage system, the page size is 1KByte and the OPTIMAL algorithm is used for page replacements. A given program has been allocated three page frames in the main memory and it makes the following 16 memory references when it starts executing (the addresses are given in decimal):500, 2000, 2500, 800, 4000, 1000, 5500, 1500, 2800, 400, 5000, 700, 2100, 3500, 900, 2400 Fill in the contents of the three page frames after each memory reference in a table and calculate the hit ratio. Hint: denote by 'a' the page consisting of locations 0 through 1023 in memory. Similarly, b: 1024-2047, c: 2048-3071, d: 3072-4095, e: 4096-5119 and f: 5120-6143. Round to three decimal places.In a certain computer, the virtual addresses are 32 bits long and the physical addresses are 48 bits long. The memory is word addressable. The page size is 16 kB and the word size is 2 bytes. The Translation Look-aside Buffer (TLB) in the address translation path has 64 valid entries. Hit ratio of TLB is 100% then maximum number of distinct virtual addresses that can be translated is K.