A processor has a 32 byte memory and an 8 byte direct-mapped cache. Table 0 shows the current state of the cache. Write hit or miss under the each address in the memory reference sequence below. Show the new state of the cache for each miss in a new table, label the table with the address, and circle the change. Tables are numbered from state 0 (intial state) to 8 (left to right in increasing order). Addr 10011 00001 00110 01010 01110 11001 00001 11100 10100 H/M Index V Tag Data Index V Tag Data 000 N 000 001 Y 00 Mem(00001) 001 010 N 010 011 Y 11 Mem(11011) 011 100 Y 10 Mem(10100) 100 Mem(01101) 101 Y 01 110 Y 00 Mem(00110) 111 N Index V 000 001 010 011 100 101 110 111 Index V 000 001 010 011 100 101 110 111 Tag Data Tag Data 101 110 111 Index V 000 001 010 011 100 101 110 111 Tag Data Index V Tag Data 000 001 010 011 100 101 110 111
A processor has a 32 byte memory and an 8 byte direct-mapped cache. Table 0 shows the current state of the cache. Write hit or miss under the each address in the memory reference sequence below. Show the new state of the cache for each miss in a new table, label the table with the address, and circle the change. Tables are numbered from state 0 (intial state) to 8 (left to right in increasing order). Addr 10011 00001 00110 01010 01110 11001 00001 11100 10100 H/M Index V Tag Data Index V Tag Data 000 N 000 001 Y 00 Mem(00001) 001 010 N 010 011 Y 11 Mem(11011) 011 100 Y 10 Mem(10100) 100 Mem(01101) 101 Y 01 110 Y 00 Mem(00110) 111 N Index V 000 001 010 011 100 101 110 111 Index V 000 001 010 011 100 101 110 111 Tag Data Tag Data 101 110 111 Index V 000 001 010 011 100 101 110 111 Tag Data Index V Tag Data 000 001 010 011 100 101 110 111
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Transcribed Image Text:(Part A)
A processor has a 32 byte memory and an 8 byte direct-mapped
cache. Table 0 shows the current state of the cache. Write hit or miss
under the each address in the memory reference sequence below.
Show the new state of the cache for each miss in a new table, label
the table with the address, and circle the change. Tables are numbered
from state 0 (intial state) to 8 (left to right in increasing order).
Addr 10011 00001 00110 01010 01110 11001 00001 11100 10100
H/M
Index V Tag Data
000 N
001
Y 00
010
N
011
Y 11
100
Y 10
101 Y 01
110
111
Index V
000
001
010
011
100
101
110
111
Y 00
N
Index V Tag Data
000
001
010
011
100
Mem(01101) 101
Mem(00110)
110
111
100
101
110
111
Mem(00001)
Mem(11011)
Mem(10100)
Tag Data
Index V Tag Data
000
001
010
011
Index V Tag Data
000
001
010
011
100
101
110
111
Index V Tag Data
000
001
010
011
100
101
110
111
Transcribed Image Text:Index V
000
001
010
011
100
101
110
111
0.
Set Tag Data
0
1
1.
(Part B)
Do the same thing as in Part A, except for a 4-way Set associative cache. Assume 00110 and 11011 were the
last two addresses to be accessed. Use the Least Recently Used replacement policy.
Set
0
1
2.
Addr 10011 00001 00110 01010 01110 11001 00001 11100 10100
H/M
Set
0
1
3.
Tag
Data
Set
0
Index V Tag Data
000
001
010
011
100
101
110
111
Tag Data
Tag Data
0011 Mem(00110)
000 Mem(00001)| 1101 Mem(11011) 0110 | Mem(01101)
Tag Data
1010 Mem(10100)
Tag Data Tag Data Tag Data Tag Data
Tag Data Tag Data Tag Data Tag Data
Tag Data Tag Data Tag Data Tag Data
4.
Set Tag Data Tag Data Tag Data Tag Data
0
1
5.
Set Tag Data Tag Data Tag
Data Tag Data
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