6 Consider a non-pipelined processor operating at2.5 GHz. It takes 5 clock cycles to complete aninstruction. You are going to make a 5-stagepipeline out of this processor. Overheadsassociated with pipelining force you to operatethe pipelined processor at 2 GHz. In a givenprogram, assume that 30% are memoryinstructions, 60% are ALU instructions and therest are branch instructions. 5% of the memoryinstructions cause stalls of 50 clock cycles eachdue to cache misses and 50% of the branchinstructions cause stalls of 2 cycles each.Assume that there are no stalls associated withthe execution of ALU instructions. For thisprogram, the speedup achieved by the pipelinedprocessor over the non-pipelined processor(round off to 2 decimal places) is

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Engineering

Computer Science

mory ons am the me ck cycl ne brar s each

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Question

Consider a non-pipelined processor operating at
2.5 GHz. It takes 5 clock cycles to complete an
instruction. You are going to make a 5-stage
pipeline out of this processor. Overheads
associated with pipelining force you to operate
the pipelined processor at 2 GHz. In a given
program, assume that 30% are memory
instructions, 60% are ALU instructions and the
rest are branch instructions. 5% of the memory
instructions cause stalls of 50 clock cycles each
due to cache misses and 50% of the branch
instructions cause stalls of 2 cycles each.
Assume that there are no stalls associated with
the execution of ALU instructions. For this
program, the speedup achieved by the pipelined
processor over the non-pipelined processor
(round off to 2 decimal places) is

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