Modify this circuit to extend the upper frequency limit to greater than 15 MHz. You may change the topology (i.e. configuration), but not the power supply voltage or collector bias current. The circuit voltage gain must be 46dB +/- 1 dB. Provide simulation results to show AC frequency responses of both circuits on the same plot, and annotate the 3dB upper frequency limit on both traces. Use typical ẞ values from the data sheet for the simulation. You may assume that 1% resistors are available in values below 100. The circuit must adhere to Standard Bias techniques. V4 Rser=0 SINE(0 0.02 10k) AC 1 VCC ୯ V2 +15V Cin1 1μ -VCC VCC R4 Rc1 147k 7k Q3 2N3904 R7 R6 9.09 20.5k Ce1 Re1 1.00k 10p Out
Modify this circuit to extend the upper frequency limit to greater than 15 MHz. You may change the topology (i.e. configuration), but not the power supply voltage or collector bias current. The circuit voltage gain must be 46dB +/- 1 dB. Provide simulation results to show AC frequency responses of both circuits on the same plot, and annotate the 3dB upper frequency limit on both traces. Use typical ẞ values from the data sheet for the simulation. You may assume that 1% resistors are available in values below 100. The circuit must adhere to Standard Bias techniques. V4 Rser=0 SINE(0 0.02 10k) AC 1 VCC ୯ V2 +15V Cin1 1μ -VCC VCC R4 Rc1 147k 7k Q3 2N3904 R7 R6 9.09 20.5k Ce1 Re1 1.00k 10p Out
Chapter55: Ac Adjustable Frequency Drives
Section: Chapter Questions
Problem 4SQ: What is the advantage of an insulated gate bipolar transistor over a common junction transistor?
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Transcribed Image Text:Modify this circuit to extend the upper frequency limit to greater than 15 MHz. You may change the
topology (i.e. configuration), but not the power supply voltage or collector bias current. The circuit
voltage gain must be 46dB +/- 1 dB. Provide simulation results to show AC frequency responses of
both circuits on the same plot, and annotate the 3dB upper frequency limit on both traces. Use
typical ẞ values from the data sheet for the simulation. You may assume that 1% resistors are
available in values below 100. The circuit must adhere to Standard Bias techniques.
V4
Rser=0
SINE(0 0.02 10k)
AC 1
VCC
୯
V2
+15V
Cin1
1μ
-VCC
VCC
R4
Rc1
147k
7k
Q3
2N3904
R7
R6
9.09
20.5k
Ce1
Re1
1.00k 10p
Out
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