CONTROL THEORY - part 2 Individual assignment Date 01.02.2019 Group N 101 Name Мерт Хатипоглу 1. Tutorial 1. Obtain the state space model of the system. Problem 1a. Consider the following block-diagram: 3 FN2212160: 3 s+1 4 s+2 y S+2 s+2s+3 Obtain the state space model of the system. 5+

For a type-1 system with input ramp signal, the value of steady state error is 0.23.  The value of velocity error constant is Answer

Determine the region where the poles of a second-order system without zeros must be so that the settling time is between 1 to 4 seconds, and the overshoot percentage is between 16.30% and 4.6%. Draw the region

Draw the graphs of the Manchester, differential Manchester, NRZ-I and NRZ-L schemes for each of the following data streams: 00110011 10101010

Derivative controller is acting on O a. Both of Transient and steady state O b. Transient and it's frequency independant OC. Steady state O d. Transient and it's frequency dependant

2- Consider the sampled data system shown below. The steady state error for unit ramp input is X T (c) (d) none of the above answers are correct R(s) + 8- The following pole-zero plot belong to. (a)stable (b)marginally stable (c)unstable (d)conditionally stable JOT (b) the system is type-1 (c) the system is type-2 (d) the system is type-3 ons WIL .... system. 3 2 1 0 -1 -2 33 ZOH @=8 * -2 -1 k s(TS +1) Ajw ·0 9-The Nyquist plot of transfer function G H(s) of a closed-loop system is given in figure below, Im (a) the system is type-0 GH-plane @=0_Re 0 Y(s) 1 2

Digital system design

Q2. It is required to design a sequence detector that detects overlapped occurrences of the sequence 10010. The circuit receives a serial input X and produces a serial output Z. The output Z will be 1 when the circuit detects the sequence 10010. Assume the existence of a reset input to reset the machine to a reset state. Draw the state diagram of the circuit assuming a Moore model. The following is an example of some input and output streams: Input X 0010010010 1 0 0 1 00 Output 0000 0 0 010010 00 0 1

V4

2:38 docs.google.com a In register indexed addressing mode, the - effective address is given by the sum of the index register value and displacement. difference of the index register value and displacement. index register value. The Data bus is a group of bidirectional 20 lines. a group of bidirectional 16 lines. a group of unidirectional 20 lines. Indicate the result of SAR BL, CL, if CL=4- and BX=FOE2H FFFEH FFE2H FOFEH Indicate thereoult of CMAP DH, AL , if-