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Modify the VHDL code in Figure 5.48 by adding a parameter that sets the number of flip-flops in the counter.

Modify the VHDL code in Figure 5.48 by adding a parameter that sets the number of flip-flops in the counter.

Introductory Circuit Analysis (13th Edition)
Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
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Modify the VHDL code in Figure 5.48 by adding a parameter that sets the number of flip-flops in the counter.
Transcribed Image Text:Modify the VHDL code in Figure 5.48 by adding a parameter that sets the number of flip-flops in the counter.
LIBRARY ieee ; USE USE ieee.std_logic_1164.all; ieee.std_logic_unsigned.all; ENTITY upcount IS PORT (Clock, Resetn, E: IN STD_LOGIC; Q END upcount; ARCHITECTURE Behavior OF upcount IS SIGNAL Count : STD_LOGIC_VECTOR (3 DOWNTO 0); BEGIN PROCESS (Clock, Resetn) BEGIN IF Resetn = '0' THEN Count <= "0000"; : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)); ELSIF (Clock'EVENT AND Clock = '1') THEN IF E = '1' THEN Count <= Count + 1; ELSE END IF; Count <= Count; END IF ; END PROCESS; Q<= Count; END Behavior; Figure 5.48 Code for a four-bit up-counter.
Transcribed Image Text:LIBRARY ieee ; USE USE ieee.std_logic_1164.all; ieee.std_logic_unsigned.all; ENTITY upcount IS PORT (Clock, Resetn, E: IN STD_LOGIC; Q END upcount; ARCHITECTURE Behavior OF upcount IS SIGNAL Count : STD_LOGIC_VECTOR (3 DOWNTO 0); BEGIN PROCESS (Clock, Resetn) BEGIN IF Resetn = '0' THEN Count <= "0000"; : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)); ELSIF (Clock'EVENT AND Clock = '1') THEN IF E = '1' THEN Count <= Count + 1; ELSE END IF; Count <= Count; END IF ; END PROCESS; Q<= Count; END Behavior; Figure 5.48 Code for a four-bit up-counter.
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