In this lab, you will design a 4-bit universal shift register that can perform right shift, left shift, and parallel loading. This shift register can be constructed using four D flip-flops and four 4-to-1 multiplexers. Parallel ounputs A Clear CLK 4x1 MUX 4x1 MUX 4x1 MUX 4x1 MUX 3210 3210 3210 Serial input for shift-right Serial -input for shil-left Paralel inputs Where: I(3:0) – Parallel Inputs Serial_in - Serial Input A(3:0) - Outputs CLK - Positive edge triggered clock S(1:0) - Select mode of register Clear - Clear register (synchronous) Below is the table showing the operation of this shift register.
In this lab, you will design a 4-bit universal shift register that can perform right shift, left shift, and parallel loading. This shift register can be constructed using four D flip-flops and four 4-to-1 multiplexers. Parallel ounputs A Clear CLK 4x1 MUX 4x1 MUX 4x1 MUX 4x1 MUX 3210 3210 3210 Serial input for shift-right Serial -input for shil-left Paralel inputs Where: I(3:0) – Parallel Inputs Serial_in - Serial Input A(3:0) - Outputs CLK - Positive edge triggered clock S(1:0) - Select mode of register Clear - Clear register (synchronous) Below is the table showing the operation of this shift register.
Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
Problem 1PE
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please write VHDL code
![In this lab, you will design a 4-bit universal shift register that can perform right shift, left
shift, and parallel loading. This shift register can be constructed using four D flip-flops and
four 4-to-1 multiplexers.
Parallel outputs
Clear
D
CLK
4x1
MUX
4x1
MUX
4x1
MUX
MUX
3210
3210
3210
Serial
input for
shift-right
Serial
input for
Paralel inputs
Where:
I(3:0) – Parallel Inputs
Serial_in - Serial Input
A(3:0) - Outputs
CLK – Positive edge triggered clock
S(1:0) – Select mode of register
Clear - Clear register (synchronous)
Below is the table showing the operation of this shift register.
S(1) S(0)
No change
Shift right (serial_in - A3, A3 - A2, A2 - A1, A1 - A0)
Shift left (A2 - A3, A1 - A2, A0 A1, serial_in A0)
Load parallel data (13 + A3, 12 - A2, I1 - A1, 10 - A0)
1
1
1
1](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2Fd53b5d21-36fa-4ee2-932f-fd40dc0982c5%2F653203ef-a03e-43d4-87b4-59a828bdc44f%2Fleurp02p_processed.jpeg&w=3840&q=75)
Transcribed Image Text:In this lab, you will design a 4-bit universal shift register that can perform right shift, left
shift, and parallel loading. This shift register can be constructed using four D flip-flops and
four 4-to-1 multiplexers.
Parallel outputs
Clear
D
CLK
4x1
MUX
4x1
MUX
4x1
MUX
MUX
3210
3210
3210
Serial
input for
shift-right
Serial
input for
Paralel inputs
Where:
I(3:0) – Parallel Inputs
Serial_in - Serial Input
A(3:0) - Outputs
CLK – Positive edge triggered clock
S(1:0) – Select mode of register
Clear - Clear register (synchronous)
Below is the table showing the operation of this shift register.
S(1) S(0)
No change
Shift right (serial_in - A3, A3 - A2, A2 - A1, A1 - A0)
Shift left (A2 - A3, A1 - A2, A0 A1, serial_in A0)
Load parallel data (13 + A3, 12 - A2, I1 - A1, 10 - A0)
1
1
1
1
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