art A. Combinational Example: 1. Practice by entering the following code for a basic two bit comparator circuit and the test bench to test it. 2. Execute the code and verify the output. 3. Modify the code to add a homework header as well as to create a 3 bit comparator circuit and an appropriate test bench to test it. 4. Execute your modified code and verify the output. // Combinational Example is a basic comparator circuit. The output z =1 if x and y are equal. module comparator( input x, input y, output z ); assign z = (~x & ~y) |(x & y); endmodule
Part A. Combinational Example:
1. Practice by entering the following code for a basic two bit comparator circuit and the test bench
to test it.
2. Execute the code and verify the output.
3. Modify the code to add a homework header as well as to create a 3 bit comparator circuit and an
appropriate test bench to test it.
4. Execute your modified code and verify the output. // Combinational Example is a basic comparator circuit. The output z =1 if x and y are equal.
module comparator(
input x,
input y,
output z
);
assign z = (~x & ~y) |(x & y);
endmodule
// testbench for comparator module
`timescale 1ns / 1ps
module stimulus;
// Inputs
reg x;
reg y;
EGS216 – Lab 8 HDL practice using online Verilog compiler.
// Outputs
wire z;
// Instantiate the Unit Under Test (UUT)
comparator uut (
.x(x),
.y(y),
.z(z)
);
initial begin // Initialize Inputs
x = 0;
y = 0;
#20 x = 1;
#20 y = 1;
#20 y = 0;
#20 x = 1;
#40;
end
initial begin
$monitor("x=%d,y=%d,z=%d \n",x,y,z);
end
endmodule
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