In this lab, you will be building a 4-bit counter using erilog. Use a 4-bit RCA, four 2-1 MUXes, and four D-type flip-flops to implement a 4-bit counter using Verilog. The counter should have Reset, Clock and Count inputs. When Reset = 0, regardless of the Count input you should observe all counter outputs to be zero (active-low reset). When Reset = 1, Count = 1 you should observe the counter outputs to increment from 0000 to 1111 one digit at a time, and then back to 0000 again, satisfying the forward counter action. Record all output values to verify the circuit logic functionality. When Reset = 1, Count = 0 you should observe the counter outputs to stall. Record the waveforms of such instances by switching Count input back-and-forth between logic 0 and logic 1 to verify the circuit logic functionality.
In this lab, you will be building a 4-bit counter using erilog. Use a 4-bit RCA, four 2-1 MUXes, and four D-type flip-flops to implement a 4-bit counter using Verilog. The counter should have Reset, Clock and Count inputs. When Reset = 0, regardless of the Count input you should observe all counter outputs to be zero (active-low reset). When Reset = 1, Count = 1 you should observe the counter outputs to increment from 0000 to 1111 one digit at a time, and then back to 0000 again, satisfying the forward counter action. Record all output values to verify the circuit logic functionality. When Reset = 1, Count = 0 you should observe the counter outputs to stall. Record the waveforms of such instances by switching Count input back-and-forth between logic 0 and logic 1 to verify the circuit logic functionality.
Computer Networking: A Top-Down Approach (7th Edition)
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Chapter1: Computer Networks And The Internet
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Write in RTL Verilog.
Use a 4-bit RCA, four 2-1 MUX, and four D-type flip-flops to implement a 4-bit counter
![In this lab, you will be building a 4-bit counter using RTL Verilog.
Use a 4-bit RCA, four 2-1 MUXes, and four D-type flip-flops to implement a 4-bit
counter using Verilog.
The counter should have Reset, Clock and Count inputs.
When Reset = 0, regardless of the Count input you should observe all counter outputs to
be zero (active-low reset).
When Reset = 1, Count = 1 you should observe the counter outputs to increment from
0000 to 1111 one digit at a time, and then back to 0000 again, satisfying the forward
counter action.
Record all output values to verify the circuit logic functionality.
When Reset = 1, Count = 0 you should observe the counter outputs to stall. Record the
waveforms of such instances by switching Count input back-and-forth between logic 0
and logic 1 to verify the circuit logic functionality.](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2Fb63cb365-95f1-4dee-a709-4120daedac93%2Fc5d46ee2-b1dd-43a5-ab83-b925e0c8d466%2Fcbbl2z_processed.png&w=3840&q=75)
Transcribed Image Text:In this lab, you will be building a 4-bit counter using RTL Verilog.
Use a 4-bit RCA, four 2-1 MUXes, and four D-type flip-flops to implement a 4-bit
counter using Verilog.
The counter should have Reset, Clock and Count inputs.
When Reset = 0, regardless of the Count input you should observe all counter outputs to
be zero (active-low reset).
When Reset = 1, Count = 1 you should observe the counter outputs to increment from
0000 to 1111 one digit at a time, and then back to 0000 again, satisfying the forward
counter action.
Record all output values to verify the circuit logic functionality.
When Reset = 1, Count = 0 you should observe the counter outputs to stall. Record the
waveforms of such instances by switching Count input back-and-forth between logic 0
and logic 1 to verify the circuit logic functionality.
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