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In this exercise, we examine how pipelining affects the clock cycle time of the processor. Problems in this exercise assume that individual stages of the datapath have the following latencies: IF ID EX MEM WB 270 ps 150 ps 240 ps 290 ps 180 ps   Also, assume that instructions executed by the processor are broken down as follows: alu beq lw sw 40% 15% 35% 10%   3.0.1       What is the clock cycle time in a pipelined and non-pipelined processor? 3.0.2       Assuming there are no stalls or hazards, what is the utilization of the data memory? 3.0.3      Instead of a single-cycle organization, we can use a multi-cycle organization where each instruction takes multiple cycles but one instruction finishes before another instruction is fetched. In this organization, an instruction only goes through stages it actually needs (e.g. ST only takes 4 cycles because it does not need the WB stage). Compare clock cycle times and execution times with single cycle, multi-cycle, and pipelined organization.

In this exercise, we examine how pipelining affects the clock cycle time of the processor. Problems in this exercise assume that individual stages of the datapath have the following latencies: IF ID EX MEM WB 270 ps 150 ps 240 ps 290 ps 180 ps   Also, assume that instructions executed by the processor are broken down as follows: alu beq lw sw 40% 15% 35% 10%   3.0.1       What is the clock cycle time in a pipelined and non-pipelined processor? 3.0.2       Assuming there are no stalls or hazards, what is the utilization of the data memory? 3.0.3      Instead of a single-cycle organization, we can use a multi-cycle organization where each instruction takes multiple cycles but one instruction finishes before another instruction is fetched. In this organization, an instruction only goes through stages it actually needs (e.g. ST only takes 4 cycles because it does not need the WB stage). Compare clock cycle times and execution times with single cycle, multi-cycle, and pipelined organization.

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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In this exercise, we examine how pipelining affects the clock cycle time of the processor. Problems in this exercise assume that individual stages of the datapath have the following latencies:

IF

ID

EX

MEM

WB

270 ps

150 ps

240 ps

290 ps

180 ps

 

Also, assume that instructions executed by the processor are broken down as follows:

alu

beq

lw

sw

40%

15%

35%

10%

 

3.0.1       What is the clock cycle time in a pipelined and non-pipelined processor?

3.0.2       Assuming there are no stalls or hazards, what is the utilization of the data memory?

3.0.3      Instead of a single-cycle organization, we can use a multi-cycle organization where each instruction takes multiple cycles but one instruction finishes before another instruction is fetched. In this organization, an instruction only goes through stages it actually needs (e.g. ST only takes 4 cycles because it does not need the WB stage). Compare clock cycle times and execution times with single cycle, multi-cycle, and pipelined organization.

M Ex. 4 U PC Address Add Instruction memory IF/D Instruction Read register 1 Read register 2 Registers Write register Write data RegWrite Instruction (15-0) Instruction (20-16) Instruction (15-11) 16 Read data 1 Read data 2 Sign- extend 32 ID/EX Shift left 2 ALUSIC 0 AddAdd result RegDst M ALU control 0 ALUOP M U Copyright © 2021 Elsevier Inc. All rights reserved Zero Add ALU result EX/MEM Branch Address Write data PCSrc MemWrite Data memory MemRead Read data MEM/WB MemtoReg IMUNO
Transcribed Image Text:M Ex. 4 U PC Address Add Instruction memory IF/D Instruction Read register 1 Read register 2 Registers Write register Write data RegWrite Instruction (15-0) Instruction (20-16) Instruction (15-11) 16 Read data 1 Read data 2 Sign- extend 32 ID/EX Shift left 2 ALUSIC 0 AddAdd result RegDst M ALU control 0 ALUOP M U Copyright © 2021 Elsevier Inc. All rights reserved Zero Add ALU result EX/MEM Branch Address Write data PCSrc MemWrite Data memory MemRead Read data MEM/WB MemtoReg IMUNO
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