In this exercise, we consider the execution of a loop in a statically scheduled superscalar processor that has full forwarding. Loop: lw $t3, 0($s1) lw $t4, 0($s2) mul $t1, $t3, $t4 add $s0, $t1, $s0 addi $s1, $s1, -8 addi $s2, $s2, -8 bne $s1, $zero, Loop Unroll this loop so that three iterations of it are done at once and schedule it for a 2-issue pipelined processor. This processor can issue one ALU/branch instruction and one lw/sw instruction each cycle. Assume that the loop always executes a number of iterations that is a multiple of 3. You can use any unused registers when changing the code to eliminate dependencies.
In this exercise, we consider the execution of a loop in a statically scheduled superscalar processor that has full forwarding.
Loop: lw $t3, 0($s1)
lw $t4, 0($s2)
mul $t1, $t3, $t4
add $s0, $t1, $s0
addi $s1, $s1, -8
addi $s2, $s2, -8
bne $s1, $zero, Loop
Unroll this loop so that three iterations of it are done at once and schedule it for a 2-issue pipelined processor. This processor can issue one ALU/branch instruction and one lw/sw instruction each cycle. Assume that the loop always executes a number of iterations that is a multiple of 3. You can use any unused registers when changing the code to eliminate dependencies.
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